Difference between revisions of "ArteryTek AT32A40x"
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| Internal flash || 0x08000000 || 1024KB || style="text-align:center;"| {{YES}} |
| Internal flash || 0x08000000 || 1024KB || style="text-align:center;"| {{YES}} |
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| − | | SPIM external flash || 0x08400000 || Up to 16 MB || style="text-align:center;"| {{ |
+ | | SPIM external flash || 0x08400000 || Up to 16 MB || style="text-align:center;"| {{YES}} |
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| + | ====SPIM external flash==== |
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| + | * For the use of SPIM, the user hast to take care, when setting up clocks, that AHB clock does not exceed 120 MHz. |
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| + | * When clocks are not setup, J-Link sets core clock to 200 MHz and AHB clock AHB to 100 MHz. |
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| + | * When clocks are not setup, J-Link sets core clock to 200 MHz and AHB clock AHB to 100 MHz. |
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The SPIM support is currently under development. |
The SPIM support is currently under development. |
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Revision as of 15:13, 20 February 2024
ArteryTek AT32A40x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | 1024KB | 
|
| SPIM external flash | 0x08400000 | Up to 16 MB |
|
SPIM external flash
- For the use of SPIM, the user hast to take care, when setting up clocks, that AHB clock does not exceed 120 MHz.
- When clocks are not setup, J-Link sets core clock to 200 MHz and AHB clock AHB to 100 MHz.
- When clocks are not setup, J-Link sets core clock to 200 MHz and AHB clock AHB to 100 MHz.
The SPIM support is currently under development.
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
