ArteryTek AT32A40x

ArteryTek AT32A40x are Cortex-M4 based MCUs

Flash Banks

Internal Flash

Flash Bank	Base address	Size	J-Link Support
Internal flash	0x08000000	1024KB
SPIM external flash	0x08400000	Up to 16 MB

SPIM external flash

• For the use of SPIM, the user hast to take care, when setting up clocks, that AHB clock does not exceed 120 MHz.
• When clocks are not setup, J-Link sets core clock to 200 MHz and AHB clock AHB to 100 MHz.
• When clocks are not setup, J-Link sets core clock to 200 MHz and AHB clock AHB to 100 MHz.

The SPIM support is currently under development.

Watchdog Handling

• The watchdog is fed during flash programming.

Device Specific Handling

Reset

• The device uses normal Cortex-M reset, no special handling necessary, like described here.

Evaluation Boards

• Artery AT-START-A403A

Example Application

• Artery AT-START-A403A