Difference between revisions of "ArteryTek AT32F41x"
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==Evaluation Boards== |
==Evaluation Boards== |
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+ | *[[ArteryTek_AT-START-F415|ArteryTek AT-START-F415]] |
==Example Application== |
==Example Application== |
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+ | *[[ArteryTek_AT-START-F413#Example_Project|ArteryTek AT-START-F413]] |
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Revision as of 16:37, 8 February 2024
ArteryTek AT32F41x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 256 KB | 
|
| SPIM external flash | 0x08400000 | Up to 16 MB | 
|
The SPIM support is currently under development.
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
