Difference between revisions of "ArteryTek AT32F41x"
(→Notes for use of SPIM external flash) |
(→Notes for use of SPIM external flash) |
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* For the use of SPIM, the user has to take care, when setting up clocks, that AHB clock does not exceed 120 MHz. |
* For the use of SPIM, the user has to take care, when setting up clocks, that AHB clock does not exceed 120 MHz. |
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* When clocks are not setup, J-Link sets core clock to 200 MHz and AHB clock to 100 MHz during SPIM flash programming. |
* When clocks are not setup, J-Link sets core clock to 200 MHz and AHB clock to 100 MHz during SPIM flash programming. |
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| − | * Only SPIM Type 2 / EN25QH128A and |
+ | * Only SPIM Type 2 / EN25QH128A and pin configuration CLK@PB1_CS@PA8_IO0@PB10_IO1@PB11_IO2@PB7_IO3_@PB6 is supported right now. |
* SPIM may not be present on all devices of this device family. |
* SPIM may not be present on all devices of this device family. |
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Revision as of 10:11, 21 February 2024
ArteryTek AT32F41x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 256 KB | 
|
| SPIM external flash | 0x08400000 | 16 MB |
|
Notes for use of SPIM external flash
- For the use of SPIM, the user has to take care, when setting up clocks, that AHB clock does not exceed 120 MHz.
- When clocks are not setup, J-Link sets core clock to 200 MHz and AHB clock to 100 MHz during SPIM flash programming.
- Only SPIM Type 2 / EN25QH128A and pin configuration CLK@PB1_CS@PA8_IO0@PB10_IO1@PB11_IO2@PB7_IO3_@PB6 is supported right now.
- SPIM may not be present on all devices of this device family.
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
