Difference between revisions of "ArteryTek AT32F41x"
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| − | + | ArteryTek AT32F41x are Cortex-M4 based MCUs |
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| Internal flash || 0x08000000 || Up to 256 KB || style="text-align:center;"| {{YES}} |
| Internal flash || 0x08000000 || Up to 256 KB || style="text-align:center;"| {{YES}} |
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+ | | User data || 0x1FFFF800 || up to 1 KB || style="text-align:center;"| {{YES}} |
| + | |- |
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| + | | SPIM external flash || 0x08400000 || 16 MB || style="text-align:center;"| {{YES}} |
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| + | ====Notes for use of SPIM external flash==== |
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| + | * For the use of SPIM, the user has to take care, when setting up clocks, that AHB clock does not exceed 120 MHz. |
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| + | * When clocks are not setup, J-Link sets core clock to 200 MHz and AHB clock to 100 MHz during SPIM flash programming. |
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| + | * Only SPIM Type 2 / EN25QH128A and pin configuration CLK@PB1_CS@PA8_IO0@PB10_IO1@PB11_IO2@PB7_IO3_@PB6 is supported right now. |
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| + | * SPIM may not be present on all devices of this device family. |
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==Watchdog Handling== |
==Watchdog Handling== |
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==Device Specific Handling== |
==Device Specific Handling== |
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| + | ===Connect=== |
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| + | *On Connect, protection level is checked. For further information regarding this, please click [[ArteryTek_AT32| here]]. |
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| + | |||
===Reset=== |
===Reset=== |
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*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | *[[ |
+ | *[[ArteryTek_AT-START-F413|ArteryTek AT-START-F413]] |
| − | *[[ |
+ | *[[ArteryTek_AT-START-F415|ArteryTek AT-START-F415]] |
==Example Application== |
==Example Application== |
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| − | *[[ |
+ | *[[ArteryTek_AT-START-F413#Example_Project|ArteryTek AT-START-F413]] |
| − | *[[ |
+ | *[[ArteryTek_AT-START-F415#Example_Project|ArteryTek AT-START-F415]] |
Latest revision as of 13:02, 18 March 2024
ArteryTek AT32F41x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 256 KB | 
|
| User data | 0x1FFFF800 | up to 1 KB |
|
| SPIM external flash | 0x08400000 | 16 MB |
|
Notes for use of SPIM external flash
- For the use of SPIM, the user has to take care, when setting up clocks, that AHB clock does not exceed 120 MHz.
- When clocks are not setup, J-Link sets core clock to 200 MHz and AHB clock to 100 MHz during SPIM flash programming.
- Only SPIM Type 2 / EN25QH128A and pin configuration CLK@PB1_CS@PA8_IO0@PB10_IO1@PB11_IO2@PB7_IO3_@PB6 is supported right now.
- SPIM may not be present on all devices of this device family.
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
