Difference between revisions of "ArteryTek AT32F42x"
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==Evaluation Boards== |
==Evaluation Boards== |
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*[[Artery_AT-START-F421|Artery AT-START-F421]] |
*[[Artery_AT-START-F421|Artery AT-START-F421]] |
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| + | *[[Artery_AT-START-F423|Artery AT-START-F423]] |
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*[[Artery_AT-START-F425|Artery AT-START-F425]] |
*[[Artery_AT-START-F425|Artery AT-START-F425]] |
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==Example Application== |
==Example Application== |
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*[[Artery_AT-START-F421#Example_Project | Artery AT-START-F421]] |
*[[Artery_AT-START-F421#Example_Project | Artery AT-START-F421]] |
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| + | *[[Artery_AT-START-F423#Example_Project | Artery AT-START-F423]] |
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*[[Artery_AT-START-F425#Example_Project | Artery AT-START-F425]] |
*[[Artery_AT-START-F425#Example_Project | Artery AT-START-F425]] |
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Revision as of 10:38, 23 January 2024
Artery AT32F42x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 64 KB | 
|
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
