Difference between revisions of "ArteryTek AT32F42x"

Revision as of 18:42, 22 January 2024

Artery AT32F42x are Cortex-M4 based MCUs

Flash Bank	Base address	Size	J-Link Support
Internal flash	0x08000000	Up to 64 KB

The device uses normal Cortex-M reset, no special handling necessary, like described here.

@@ Line 1: / Line 1: @@
-Artery AT32F43x are Cortex-M4 based MCUs
+Artery AT32F42x are Cortex-M4 based MCUs
 __TOC__
@@ Line 8: / Line 8: @@
 ! Flash Bank || Base address !! Size || J-Link Support
 |-
-| Internal flash || 0x08000000 || Up to 4096 KB || style="text-align:center;"| {{YES}}
+| Internal flash || 0x08000000 || Up to 64 KB || style="text-align:center;"| {{YES}}
-|}
-===QSPI Flash===
-QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br>
-J-Link supports multiple pin configurations for AT32F43x. The default loader is marked in '''bold'''.
-{| class="seggertable"
-|-
-! Device !! Base address !! Maximum size !! Supported pin configuration
-|-
-| '''QSPI1'''<br>
-AT32F435<br>
-AT32F437
-|| 0x90000000  || Up to 64 MB ||
-*'''CLK@PF10 CS@PG6 IO0@PF9 IO1@PF8 IO2@PF7 IO3_@PF6'''
 |}
@@ Line 33: / Line 19: @@
 ==Evaluation Boards==
-*[[Artery_AT-START-F435|Artery AT-START-F435]]
+*[[Artery_AT-START-F425|Artery AT-START-F425]]
-*[[Artery_AT-START-F437|Artery AT-START-F437]]
 ==Example Application==
-*[[Artery_AT-START-F435#Example_Project | Artery AT-START-F435]]
+*[[Artery_AT-START-F425#Example_Project | Artery AT-START-F425]]
 *[[Artery_AT-START-F437#Example_Project | Artery AT-START-F437]]