Difference between revisions of "ArteryTek AT32WB41x"
m (Torben.scharping moved page Artery AT32WB41x to ArteryTek AT32WB41x) |
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| Internal flash || 0x08000000 || 256 KB || style="text-align:center;"| {{YES}} |
| Internal flash || 0x08000000 || 256 KB || style="text-align:center;"| {{YES}} |
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+ | | User data || 0x1FFFF800 || 1 KB || style="text-align:center;"| {{YES}} |
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==Device Specific Handling== |
==Device Specific Handling== |
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+ | ===Connect=== |
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+ | *On Connect, protection level is checked. For further information regarding this, please click [[ArteryTek_AT32| here]]. |
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===Reset=== |
===Reset=== |
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*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
Revision as of 12:59, 18 March 2024
ArteryTek AT32WB41x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Internal flash | 0x08000000 | 256 KB | |
User data | 0x1FFFF800 | 1 KB |
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Evaluation Boards