Difference between revisions of "ArteryTek AT32WB41x"
m (Torben.scharping moved page Artery AT32WB413 to Artery AT32WB41x) |
|||
| Line 1: | Line 1: | ||
| − | Artery |
+ | Artery AT32WB41x are Cortex-M4 based MCUs |
__TOC__ |
__TOC__ |
||
| Line 19: | Line 19: | ||
==Evaluation Boards== |
==Evaluation Boards== |
||
| − | *[[Artery_AT-START- |
+ | *[[Artery_AT-START-WB415|Artery AT-START-WB415]] |
==Example Application== |
==Example Application== |
||
| − | *[[Artery_AT-START- |
+ | *[[Artery_AT-START-WB415#Example_Project|Artery AT-START-WB415]] |
Revision as of 11:03, 2 February 2024
Artery AT32WB41x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | 256 KB | 
|
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Evaluation Boards
