Difference between revisions of "Cmsemicon CM32H6157"
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! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
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| − | | Main flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES |
+ | | Main flash || 0x00000000 || 128 KB || style="text-align:center;"| {{YES}} |
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| − | | Data flash || 0x00000000 || 2560 B || style="text-align:center;"| {{YES |
+ | | Data flash || 0x00000000 || 2560 B || style="text-align:center;"| {{YES}} |
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| + | <br> |
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| + | {{Note|The option bytes are located in Main flash from 0x000000C0 to 0x000000C4.<br> Please ensure the correct settings.}} |
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==Watchdog Handling== |
==Watchdog Handling== |
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==Device Specific Handling== |
==Device Specific Handling== |
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| − | ===Connect=== |
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===Reset=== |
===Reset=== |
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*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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Latest revision as of 08:05, 11 March 2024
The Cmsemicon CM32H6157 are are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M0 processor.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash | 0x00000000 | 128 KB | 
|
| Data flash | 0x00000000 | 2560 B |
|
Note:
The option bytes are located in Main flash from 0x000000C0 to 0x000000C4.
Please ensure the correct settings.
The option bytes are located in Main flash from 0x000000C0 to 0x000000C4.
Please ensure the correct settings.
Watchdog Handling
- The device has a watchdog.
- The watchdog is fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
