Difference between revisions of "Cmsemicon CM32H6157"
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*The watchdog is fed during flash programming. |
*The watchdog is fed during flash programming. |
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| − | ==Device Specific Handling== |
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| − | ===Connect=== |
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===Reset=== |
===Reset=== |
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*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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Revision as of 08:00, 11 March 2024
The Cmsemicon CM32H6157 are are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M0 processor.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash | 0x00000000 | 128 KB |  / 
|
| Data flash | 0x00000000 | 2560 B | /
|
Watchdog Handling
- The device has a watchdog.
- The watchdog is fed during flash programming.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
