Difference between revisions of "Codasip L10"
(Created page with "The Codasip L10 is a 32-bit (RV32) core, designed by [https://codasip.com/products/codasip-risc-v-processors/ Codasip]. __TOC__ = Minimum required J-Link software version =...") |
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= RTT support = |
= RTT support = |
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| + | * RTT is automatically supported by J-Link if the core supports system bus access (SBA) |
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| − | As the core does not support System Bus Access (SBA), RTT is not supported for this core. |
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| + | * As SBA is a configuration option of the core, the configuration option must be chosen to have RTT support |
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| − | = HSS |
+ | = HSS support = |
| + | See RTT. |
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| − | As the core does not support System Bus Access (SBA), HSS is not supported for this core. |
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Latest revision as of 10:19, 15 June 2021
The Codasip L10 is a 32-bit (RV32) core, designed by Codasip.
Minimum required J-Link software version
The L10 device selection is supported since V7.24 of the J-Link software.
RTT support
- RTT is automatically supported by J-Link if the core supports system bus access (SBA)
- As SBA is a configuration option of the core, the configuration option must be chosen to have RTT support
HSS support
See RTT.
