Difference between revisions of "Flasher ARM V5"

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(→‎Hardware and Software Features)
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__TOC__
  
__TOC__
   
−
== Hardware and Software Features ==
 +
== Hardware Features ==
−
{| class="wikitable"
 +
{| class="seggertable"
−
|+
  
 
|-
  
|-
−
! style="position:sticky; top:0"|Hardware version
 +
!style="position:sticky; top:0"|Feature !!style="position:sticky; top:0"| S !!style="position:sticky; top:0"| PC
−
!colspan=2; style="position:sticky; top:0"|5
  
 
|-
  
|-
  +
!colspan=3| S = Standalone mode; PC = PC-based mode
−
! style="position:sticky; top:0"|Operating mode**
  
−
! style="position:sticky; top:0"|S
  
−
! style="position:sticky; top:0"|PC
  
 
|-
  
|-
  +
| USB 2.0 Full Speed ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
−
!colspan=3;| Operating Mode** S = Standalone; PC = PC-based
  
 
|-
  
|-
−
|- style="text-align:center"
 +
| Ethernet ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
−
|colspan="3"| Hardware Features
  
 
|-
  
|-
−
! style="text-align:left;"|USB 2.0 Full Speed || {{YES}} || {{YES}}
 +
| JTAG interface ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Ethernet || {{YES}} || {{YES}}
 +
| cJTAG interface ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|JTAG interface || {{YES}} || {{YES}}
 +
| cJTAG interface without/buggy KEEPER logic ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|cJTAG interface || {{YES}} || {{YES}}
 +
| SWD interface ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|cJTAG interface without/buggy KEEPER logic || {{YES}} || {{YES}}
 +
| SWO interface ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|SWD interface || {{YES}} || {{YES}}
 +
| SPI interface ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|SWO interface || {{YES}} || {{YES}}
 +
| QSPI interface ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|SPI interface || {{YES}} || {{YES}}
 +
| Microchip PIC32 ICSP interface ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|QSPI interface || {{NO}} || {{NO}}
 +
| Renesas FINE interface ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|Microchip PIC32 ICSP interface || {{NO}} || {{NO}}
 +
| SiLabs C2 2-wire interface ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|Renesas FINE interface || {{NO}} || {{NO}}
 +
| ETB Trace ARM7/9 ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|SiLabs C2 2-wire interface || {{NO}} || {{NO}}
 +
| ETB Trace Cortex-M ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|ETB Trace ARM7/9 || {{YES}} || {{YES}}
 +
| ETB Trace Cortex-A/R ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|ETB Trace Cortex-M || {{YES}} || {{YES}}
 +
| ETM Trace Cortex-M ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|ETB Trace Cortex-A/R || {{YES}} || {{YES}}
 +
| ETM Trace Cortex-A ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|ETM Trace Cortex-M || {{NO}} || {{NO}}
 +
| VCOM ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|ETM Trace Cortex-A || {{NO}} || {{NO}}
 +
| Memory Stop mode support ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|VCOM || {{NO}} || {{NO}}
 +
| Cortex-M Monitor Mode debugging ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|Memory Stop mode support || {{YES}} || {{YES}}
 +
| SWD Multi-Drop ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M Monitor Mode debugging || {{NO}} || {{NO}}
 +
| CMSIS-DAP mode ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
  +
|}
  +
  +
  +
J-Link provides debugging support for the following cores.<br>
  +
{{Note|1=If you are interested in J-Link support for a core that is not listed here, please feel free to request support via the [https://www.segger.com/ticket SEGGER support ticket system].}}
  +
  +
{| class="seggertable"
 
|-
  
|-
  +
!style="position:sticky; top:0"|Core !!style="position:sticky; top:0"| S !!style="position:sticky; top:0"| PC
−
! style="text-align:left;"|SWD Multi-Drop || {{YES}} || {{YES}}
  
 
|-
  
|-
  +
!colspan=3| S = Standalone mode; PC = PC-based mode
−
! style="text-align:left;"|CMSIS-DAP mode || {{NO}} || {{NO}}
  
−
|- style="text-align:center"
  
−
|colspan="3"| ARM legacy Cores
  
 
|-
  
|-
  +
!colspan="3"| ARM legacy Cores
−
! style="text-align:left;"|ARM7 || {{YES}} || {{YES}}
 
 
|-
  
|-
−
! style="text-align:left;"|ARM9 || {{YES}} || {{YES}}
+
| ARM7 ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|ARM11 || {{NO}} || {{NO}}
+
| ARM9 ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
−
|- style="text-align:center"
  
−
|colspan="3"| ARM Cortex Cores
  
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A5 || {{NO}} || {{YES}}
+
| ARM11 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
  +
!colspan="3"| ARM Cortex Cores
−
! style="text-align:left;"|Cortex-A7 || {{NO}} || {{YES}}
 
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A8 || {{NO}} || {{YES}}
+
| Cortex-A5 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A9 || {{NO}} || {{YES}}
+
| Cortex-A7 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A12 || {{NO}} || {{YES}}
+
| Cortex-A8 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A15 || {{NO}} || {{YES}}
+
| Cortex-A9 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A17 || {{NO}} || {{YES}}
+
| Cortex-A12 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A53 || {{NO}} || {{NO}}
+
| Cortex-A15 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A55 || {{NO}} || {{NO}}
+
| Cortex-A17 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A57 || {{NO}} || {{NO}}
+
| Cortex-A53 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-A72 || {{NO}} || {{NO}}
+
| Cortex-A55 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M0 || {{YES}} || {{YES}}
+
| Cortex-A57 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M0+ || {{YES}} || {{YES}}
+
| Cortex-A72 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M1 || {{YES}} || {{YES}}
+
| Cortex-M0 ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M3 || {{YES}} || {{YES}}
+
| Cortex-M0+ ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M4 || {{YES}} || {{YES}}
+
| Cortex-M1 ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M7 || {{YES}} || {{YES}}
+
| Cortex-M3 ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M23 || {{YES}} || {{YES}}
+
| Cortex-M4 ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-M33 || {{YES}} || {{YES}}
+
| Cortex-M7 ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-R4 || {{NO}} || {{YES}}
+
| Cortex-M23 ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-R5 || {{NO}} || {{YES}}
+
| Cortex-M33 ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|Cortex-R8 || {{NO}} || {{YES}}
+
| Cortex-R4 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|SC000 (M0 secure) || {{YES}} || {{YES}}
+
| Cortex-R5 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|SC300 (M3 secure) || {{YES}} || {{YES}}
+
| Cortex-R8 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{YES}}
−
|- style="text-align:center"
  
−
|colspan="3"| RISC-V
  
 
|-
  
|-
−
! style="text-align:left;"|RV32 || {{NO}} || {{NO}}
+
| SC000 (M0 secure) ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
 
|-
  
|-
−
! style="text-align:left;"|RV64 || {{NO}} || {{NO}}
+
| SC300 (M3 secure) ||style="text-align:center;"| {{YES}} ||style="text-align:center;"| {{YES}}
−
|- style="text-align:center"
  
−
|colspan="3"| Microchip PIC32
  
 
|-
  
|-
  +
!colspan="3"| RISC-V
−
! style="text-align:left;"|PIC32MX || {{NO}} || {{NO}}
 
 
|-
  
|-
−
! style="text-align:left;"|PIC32MZ || {{NO}} || {{NO}}
+
| RV32 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
−
|- style="text-align:center"
  
−
|colspan="3"| SiLabs 8051
  
 
|-
  
|-
−
! style="text-align:left;"|EFM8 || {{NO}} || {{NO}}
+
| RV64 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
−
|- style="text-align:center"
  
−
|colspan="3"| Renesas RX
  
 
|-
  
|-
  +
!colspan="3"| Microchip PIC32
−
! style="text-align:left;"|RX110 || {{NO}} || {{NO}}
 
 
|-
  
|-
−
! style="text-align:left;"|RX111 || {{NO}} || {{NO}}
+
| PIC32MX ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX210 || {{NO}} || {{NO}}
+
| PIC32MZ ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
  +
!colspan="3"| SiLabs 8051
−
! style="text-align:left;"|RX21A || {{NO}} || {{NO}}
 
 
|-
  
|-
−
! style="text-align:left;"|RX220 || {{NO}} || {{NO}}
+
| EFM8 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
  +
!colspan="3"| Renesas RX
−
! style="text-align:left;"|RX610 || {{NO}} || {{NO}}
 
 
|-
  
|-
−
! style="text-align:left;"|RX621 || {{NO}} || {{NO}}
+
| RX110 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX62G || {{NO}} || {{NO}}
+
| RX111 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX62N || {{NO}} || {{NO}}
+
| RX210 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX62T || {{NO}} || {{NO}}
+
| RX21A ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX630 || {{NO}} || {{NO}}
+
| RX220 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX631 || {{NO}} || {{NO}}
+
| RX610 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX63N || {{NO}} || {{NO}}
+
| RX621 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX63T || {{NO}} || {{NO}}
+
| RX62G ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|-
  
|-
−
! style="text-align:left;"|RX64M || {{NO}} || {{NO}}
 +
| RX62N ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
  +
|-
  +
| RX62T ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
  +
|-
  +
| RX630 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
  +
|-
  +
| RX631 ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
  +
|-
  +
| RX63N ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
  +
|-
  +
| RX63T ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
  +
|-
  +
| RX64M ||style="text-align:center;"| {{NO}} ||style="text-align:center;"| {{NO}}
 
|}
  
|}

Revision as of 16:42, 20 December 2022

This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER Flasher ARM V5.

Hardware Features

Feature S PC
S = Standalone mode; PC = PC-based mode
USB 2.0 Full Speed YES.png YES.png
Ethernet YES.png YES.png
JTAG interface YES.png YES.png
cJTAG interface YES.png YES.png
cJTAG interface without/buggy KEEPER logic YES.png YES.png
SWD interface YES.png YES.png
SWO interface YES.png YES.png
SPI interface YES.png YES.png
QSPI interface NO.png NO.png
Microchip PIC32 ICSP interface NO.png NO.png
Renesas FINE interface NO.png NO.png
SiLabs C2 2-wire interface NO.png NO.png
ETB Trace ARM7/9 YES.png YES.png
ETB Trace Cortex-M YES.png YES.png
ETB Trace Cortex-A/R YES.png YES.png
ETM Trace Cortex-M NO.png NO.png
ETM Trace Cortex-A NO.png NO.png
VCOM NO.png NO.png
Memory Stop mode support YES.png YES.png
Cortex-M Monitor Mode debugging NO.png NO.png
SWD Multi-Drop YES.png YES.png
CMSIS-DAP mode NO.png NO.png


J-Link provides debugging support for the following cores.

Note:
If you are interested in J-Link support for a core that is not listed here, please feel free to request support via the SEGGER support ticket system.
Core S PC
S = Standalone mode; PC = PC-based mode
ARM legacy Cores
ARM7 YES.png YES.png
ARM9 YES.png YES.png
ARM11 NO.png NO.png
ARM Cortex Cores
Cortex-A5 NO.png YES.png
Cortex-A7 NO.png YES.png
Cortex-A8 NO.png YES.png
Cortex-A9 NO.png YES.png
Cortex-A12 NO.png YES.png
Cortex-A15 NO.png YES.png
Cortex-A17 NO.png YES.png
Cortex-A53 NO.png NO.png
Cortex-A55 NO.png NO.png
Cortex-A57 NO.png NO.png
Cortex-A72 NO.png NO.png
Cortex-M0 YES.png YES.png
Cortex-M0+ YES.png YES.png
Cortex-M1 YES.png YES.png
Cortex-M3 YES.png YES.png
Cortex-M4 YES.png YES.png
Cortex-M7 YES.png YES.png
Cortex-M23 YES.png YES.png
Cortex-M33 YES.png YES.png
Cortex-R4 NO.png YES.png
Cortex-R5 NO.png YES.png
Cortex-R8 NO.png YES.png
SC000 (M0 secure) YES.png YES.png
SC300 (M3 secure) YES.png YES.png
RISC-V
RV32 NO.png NO.png
RV64 NO.png NO.png
Microchip PIC32
PIC32MX NO.png NO.png
PIC32MZ NO.png NO.png
SiLabs 8051
EFM8 NO.png NO.png
Renesas RX
RX110 NO.png NO.png
RX111 NO.png NO.png
RX210 NO.png NO.png
RX21A NO.png NO.png
RX220 NO.png NO.png
RX610 NO.png NO.png
RX621 NO.png NO.png
RX62G NO.png NO.png
RX62N NO.png NO.png
RX62T NO.png NO.png
RX630 NO.png NO.png
RX631 NO.png NO.png
RX63N NO.png NO.png
RX63T NO.png NO.png
RX64M NO.png NO.png
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