Difference between revisions of "GD32VF103"
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| − | The GigaDevice |
+ | The GigaDevice GD32VF103 series is the first member of the GigaDevice [[GD32V]] RISC-V MCU family. |
| − | = Available eval boards = |
+ | == Available eval boards == |
The following eval boards that are based on the GD32VF1xx are available: |
The following eval boards that are based on the GD32VF1xx are available: |
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* GD32VF103V-EVAL Rev 1 |
* GD32VF103V-EVAL Rev 1 |
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| + | * [https://wiki.segger.com/SiPeed_Longan_Nano SiPeed Longan Nano] |
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| − | * Boardlink |
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| + | |||
| + | == Reset == |
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| + | On the Gigadevice GD32VF1 series devices, the ndmreset bit of the RISC-V debug interface does not reset the peripherals. |
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| + | It is not clear if it resets the core reliably as well. Therefore, if a GD32VF1 series device is selected, J-Link by default uses the reset pin to reset the chip. |
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| + | |||
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Latest revision as of 17:15, 7 December 2023
Contents
The GigaDevice GD32VF103 series is the first member of the GigaDevice GD32V RISC-V MCU family.
Available eval boards
The following eval boards that are based on the GD32VF1xx are available:
- GD32VF103V-EVAL Rev 1
- SiPeed Longan Nano
Reset
On the Gigadevice GD32VF1 series devices, the ndmreset bit of the RISC-V debug interface does not reset the peripherals. It is not clear if it resets the core reliably as well. Therefore, if a GD32VF1 series device is selected, J-Link by default uses the reset pin to reset the chip.
