Difference between revisions of "GigaDevice GD32C1"
| Line 17: | Line 17: | ||
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| + | ==Watchdog Handling== |
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| + | *The device does have 2 watchdogs. |
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| + | *The watchdogs are fed during flash programming. |
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| + | ==Device Specific Handling== |
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| − | ==Reset== |
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| + | ===Connect=== |
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| − | No special reset is required. |
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| + | *On Connect, protection level is checked. For further information regarding this, please click [[GigaDevice_GD32| here]]. |
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| + | |||
| + | ===Reset=== |
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| + | *The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | *GigaDevice GD32C113C |
+ | *[[GigaDevice_GD32C113C-START| GigaDevice GD32C113C START]] |
==Example Application== |
==Example Application== |
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| − | * |
+ | *[[GigaDevice_GD32C113C-START#Example_Project | GigaDevice GD32C113C START]] |
Revision as of 16:22, 16 February 2024
The GigaDevice GD32C1 series are 32-bit general-purpose microcontrollers based on the ARM Cortex-M4 processor.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash | 0x08000000 | Up to 256 KB | 
|
| Information flash | 0x1FFFB000 | 18 KB | 
|
| Option Bytes | 0x1FFFF800 | 16 B |
|
| OTP | 0x1FFF7000 | 512 B |
|
Watchdog Handling
- The device does have 2 watchdogs.
- The watchdogs are fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
