Difference between revisions of "GigaDevice GD32C1"
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! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
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| − | | Main flash || 0x08000000 || |
+ | | Main flash || 0x08000000 || 128 KB || style="text-align:center;"| {{YES}} |
| − | |- |
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| − | | Information flash || 0x1FFFB000|| 18 KB || style="text-align:center;"| {{NO}} |
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|- |
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| Option Bytes || 0x1FFFF800 || 16 B || style="text-align:center;"| {{YES}} |
| Option Bytes || 0x1FFFF800 || 16 B || style="text-align:center;"| {{YES}} |
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|- |
|- |
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| − | | OTP || 0x1FFF7000 || 512 B || style="text-align:center;"| {{NO}} |
+ | | OTP Bytes || 0x1FFF7000 || 512 B || style="text-align:center;"| {{NO}} |
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|} |
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| + | ==Watchdog Handling== |
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| − | ==On-Chip Memory Regions== |
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| + | *The device does have 2 watchdogs, FWDGT and WWDGT. |
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| − | The internal flash is divided into 4 different regions:<br> |
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| + | *The WWDGT watchdog is fed during flash programming. |
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| − | *Main Flash Block (0x08000000 - 0x0801FFFF) |
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| − | *Information Block (0x1FFFB000 - 0x1FFFF7FF) |
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| − | *Option bytes Block (0x1FFFF800 - 0x1FFFF80F) |
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| − | *One-time program Block (0x1FFF7000 - 0x1FFF71FF) |
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| + | ==Device Specific Handling== |
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| − | For now, the Main Flash Block is supported, only. |
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| + | ===Connect=== |
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| + | *On Connect, protection level is checked. For further information regarding this, please click [[GigaDevice_GD32| here]]. |
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| − | ==Reset== |
+ | ===Reset=== |
| + | *The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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| − | No special reset is required. |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | *GigaDevice GD32C113C |
+ | *[[GigaDevice_GD32C113C-START| GigaDevice GD32C113C START]] |
==Example Application== |
==Example Application== |
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| − | * |
+ | *[[GigaDevice_GD32C113C-START#Example_Project | GigaDevice GD32C113C START]] |
Latest revision as of 15:35, 22 February 2024
The GigaDevice GD32C1 series are 32-bit general-purpose microcontrollers based on the ARM Cortex-M4 processor.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash | 0x08000000 | 128 KB | 
|
| Option Bytes | 0x1FFFF800 | 16 B |
|
| OTP Bytes | 0x1FFF7000 | 512 B | 
|
Watchdog Handling
- The device does have 2 watchdogs, FWDGT and WWDGT.
- The WWDGT watchdog is fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
