Difference between revisions of "Infineon CY-SD2220"
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== Preparing for J-Link == |
== Preparing for J-Link == |
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− | *Connect the J-Link to |
+ | *Connect the J-Link to J18: |
+ | **GND on J18.2 |
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− | *Power the board via........ |
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+ | **SWDIO on J18.5 |
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+ | **SWCLK on J18.4 |
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+ | **Reset on J18.3 |
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+ | **VTref on TP13 |
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+ | *Power the board via J5. |
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* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
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+ | [[File:Infineon__CY-SD2220_Rev01_CYPD7191-40LDXS_connect.png|400px]] |
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− | '''[PICTURE OF CONNECT]''' |
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− | [[File:VENDOR_DEVICE_CONNECT.PNG|400px]] |
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== Example Project== |
== Example Project== |
Revision as of 12:49, 27 December 2023
This article describes specifics for the Infineon CY-SD2220 evaluation board.
[PICTURE OF BOARD]
450px
Preparing for J-Link
- Connect the J-Link to J18:
- GND on J18.2
- SWDIO on J18.5
- SWCLK on J18.4
- Reset on J18.3
- VTref on TP13
- Power the board via J5.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Infineon CY-SD2220.
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.xx
- Embedded Studio: V7.20
- Hardware: [SiliconVendor] [EvalBoardName]
- Link: File:VENDOR DEVICENAME TestProject ES V452b.zip