Difference between revisions of "Infineon CYT2B9"
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'''CYT2B9 (TVII-B-E-2M)''' is a subfamily of [[Infineon Traveo II device family | Traveo II]] microcontrollers containing a Cortex M4 and Cortex M0+ CPU. |
'''CYT2B9 (TVII-B-E-2M)''' is a subfamily of [[Infineon Traveo II device family | Traveo II]] microcontrollers containing a Cortex M4 and Cortex M0+ CPU. |
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+ | == SRAM == |
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+ | The CYT2B9 family features 2 x 128 KB = 256 KB of SRAM located at 0x08000000. The first 2 KB are reserved for internal usage and may not be used. |
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== Flash memory layout == |
== Flash memory layout == |
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The CYT2B9 series devices have 2112 KiB Code flash and a 128 KiB Work flash. Both flashes are split in an area of large sectors and an area of small sectors. |
The CYT2B9 series devices have 2112 KiB Code flash and a 128 KiB Work flash. Both flashes are split in an area of large sectors and an area of small sectors. |
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Revision as of 16:30, 14 February 2022
CYT2B9 (TVII-B-E-2M) is a subfamily of Traveo II microcontrollers containing a Cortex M4 and Cortex M0+ CPU.
SRAM
The CYT2B9 family features 2 x 128 KB = 256 KB of SRAM located at 0x08000000. The first 2 KB are reserved for internal usage and may not be used.
Flash memory layout
The CYT2B9 series devices have 2112 KiB Code flash and a 128 KiB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.
Flash | Start adress | End adress | Sector size | Sector count | Total size |
---|---|---|---|---|---|
Code flash large area | 0x10000000 | 0x101EFFFF | 32 KiB | 62 | 1984 KiB |
Code flash small area | 0x101F0000 | 0x1010FFFF | 8 KiB | 16 | 128 KiB |
Work flash large area | 0x14000000 | 0x14017FFF | 2 KiB | 48 | 96 KiB |
Work flash small area | 0x14018000 | 0x1401FFFF | 128 B | 256 | 32 KiB |