Difference between revisions of "Infineon CYT4BF"
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| Work flash small area || 0x14030000 || 0x1403FFFF || 128 B || 512 || 64 KiB |
| Work flash small area || 0x14030000 || 0x1403FFFF || 128 B || 512 || 64 KiB |
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| + | == Trace == |
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| + | For more information regarding trace for this device, see [[Tracing on Infineon Traveo II (CYT4BF) | Tracing on Infineon Traveo II (CYT4BF)]] |
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Revision as of 10:25, 12 January 2023
CYT4BF (TVII-B-H-8M) is a subfamily of Traveo II microcontrollers containing a Cortex M7 and Cortex M0+ CPU.
SRAM
The CYT4BF family features 512 KB + 2 x 256 KB = 1024 KB of SRAM located at 0x28000000. The first 2 KB are reserved for internal usage and may not be used.
Flash memory layout
The CYT4BF series devices have 8384 KiB Code flash and a 256 KiB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.
| Flash | Start adress | End adress | Sector size | Sector count | Total size |
|---|---|---|---|---|---|
| Code flash large area | 0x10000000 | 0x107EFFFF | 32 KiB | 254 | 8128 KiB |
| Code flash small area | 0x107F0000 | 0x1082FFFF | 8 KiB | 32 | 256 KiB |
| Work flash large area | 0x14000000 | 0x1402FFFF | 2 KiB | 96 | 192 KiB |
| Work flash small area | 0x14030000 | 0x1403FFFF | 128 B | 512 | 64 KiB |
Trace
For more information regarding trace for this device, see Tracing on Infineon Traveo II (CYT4BF)
