Difference between revisions of "J-Link LITE ARM V9"
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− | == Hardware |
+ | == Hardware Features == |
− | {| class=" |
+ | {| class="seggertable" |
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+ | ! Feature !! Supported |
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− | ! style="position:sticky; top:0"|Hardware version |
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− | ! style="position:sticky; top:0"|9 |
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− | |- style="text-align:center" |
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− | |colspan="7"| Hardware Features |
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− | + | | USB 2.0 Full Speed ||style="text-align:center;"| {{YES}} |
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− | + | | JTAG interface ||style="text-align:center;"| {{YES}} |
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− | + | | SWD interface ||style="text-align:center;"| {{YES}} |
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− | + | | SWO interface ||style="text-align:center;"| {{YES}} |
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− | + | | SPI interface ||style="text-align:center;"| {{NO}} |
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− | + | | QSPI interface ||style="text-align:center;"| {{NO}} |
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− | + | | Microchip ICSP interface ||style="text-align:center;"| {{NO}} |
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− | + | | Renesas FINE interface ||style="text-align:center;"| {{NO}} |
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− | + | | SiLabs C2 2-wire interface ||style="text-align:center;"| {{NO}} |
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− | + | | ETB Trace ARM7/9 ||style="text-align:center;"| {{YES}} |
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− | + | | ETB Trace Cortex-M ||style="text-align:center;"| {{YES}} |
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− | + | | ETB Trace Cortex-A/R ||style="text-align:center;"| {{YES}} |
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− | + | | ETM Trace Cortex-M ||style="text-align:center;"| {{NO}} |
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− | + | | VCOM ||style="text-align:center;"| {{NO}} |
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− | + | | Memory Stop mode support ||style="text-align:center;"| {{YES}} |
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+ | | Cortex-M Monitor Mode debugging ||style="text-align:center;"| {{NO}} |
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+ | |- |
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+ | | SWD Multi-Drop ||style="text-align:center;"| {{NO}} |
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+ | |- |
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+ | | CMSIS-DAP mode ||style="text-align:center;"| {{NO}} |
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+ | |- |
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+ | |} |
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+ | == Supported cores == |
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− | ! style="text-align:left;"|Cortex-M Monitor Mode debugging || {{NO}} |
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+ | J-Link provides debugging support for the following cores.<br> |
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+ | {{Note|1=If you are interested in J-Link support for a core that is not listed here, please feel free to request support via the [https://www.segger.com/ticket SEGGER support ticket system].}} |
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+ | |||
+ | {| class="seggertable" |
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+ | |- |
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+ | ! Core !! Supported |
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+ | |- |
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+ | !colspan="2"| ARM legacy Cores |
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+ | |- |
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+ | | ARM7 ||style="text-align:center;"| {{YES}} |
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+ | |- |
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+ | | ARM9 ||style="text-align:center;"| {{YES}} |
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+ | |- |
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+ | | ARM11 ||style="text-align:center;"| {{YES}} |
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+ | !colspan="2"| ARM Cortex Cores |
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− | ! style="text-align:left;"|SWD Multi-Drop || {{NO}} |
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− | + | | Cortex-A5 ||style="text-align:center;"| {{YES}} |
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− | |- style="text-align:center" |
+ | | Cortex-A7 ||style="text-align:center;"| {{YES}} |
− | |colspan="7"| ARM legacy Cores |
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− | + | | Cortex-A8 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-A9 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-A12 ||style="text-align:center;"| {{YES}} |
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− | |- style="text-align:center" |
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− | |colspan="7"| ARM Cortex Cores |
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− | + | | Cortex-A15 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-A17 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-A53 ||style="text-align:center;"| {{NO}} |
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− | + | | Cortex-A55 ||style="text-align:center;"| {{NO}} |
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− | + | | Cortex-A57 ||style="text-align:center;"| {{NO}} |
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− | + | | Cortex-A72 ||style="text-align:center;"| {{NO}} |
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− | + | | Cortex-M0 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M0+ ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M1 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M3 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M4 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M7 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M23 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-M33 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-R4 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-R5 ||style="text-align:center;"| {{YES}} |
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− | + | | Cortex-R8 ||style="text-align:center;"| {{YES}} |
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− | + | | SC000 (M0 secure) ||style="text-align:center;"| {{YES}} |
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− | + | | SC300 (M3 secure) ||style="text-align:center;"| {{YES}} |
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+ | !colspan="2"| RISC-V |
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− | ! style="text-align:left;"|Cortex-R5 || {{YES}} |
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− | + | | RV32 ||style="text-align:center;"| {{NO}} |
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− | + | | RV64 ||style="text-align:center;"| {{NO}} |
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− | ! style="text-align:left;"|SC300 (M3 secure) || {{YES}} |
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− | |- style="text-align:center" |
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− | |colspan="7"| RISC-V |
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+ | !colspan="2"| Microchip PIC32 |
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− | ! style="text-align:left;"|RV32 || {{NO}} |
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− | + | | PIC32MX ||style="text-align:center;"| {{NO}} |
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− | | |
+ | | PIC32MZ ||style="text-align:center;"| {{NO}} |
− | |colspan="7"| Microchip PIC32 |
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+ | !colspan="2"| SiLabs 8051 |
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− | ! style="text-align:left;"|PIC32MX || {{NO}} |
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− | + | | EFM8 ||style="text-align:center;"| {{NO}} |
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− | |- style="text-align:center" |
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− | |colspan="7"| SiLabs 8051 |
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− | ! style="text-align:left;"|EFM8 || {{NO}} |
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+ | !colspan="2"| Renesas RX |
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− | |- style="text-align:center" |
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− | |colspan="7"| Renesas RX |
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− | + | | RX110 ||style="text-align:center;"| {{NO}} |
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− | + | | RX111 ||style="text-align:center;"| {{NO}} |
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− | + | | RX210 ||style="text-align:center;"| {{NO}} |
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− | + | | RX21A ||style="text-align:center;"| {{NO}} |
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− | + | | RX220 ||style="text-align:center;"| {{NO}} |
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− | + | | RX610 ||style="text-align:center;"| {{NO}} |
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− | + | | RX621 ||style="text-align:center;"| {{NO}} |
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− | + | | RX62G ||style="text-align:center;"| {{NO}} |
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− | + | | RX62G ||style="text-align:center;"| {{NO}} |
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− | + | | RX62N ||style="text-align:center;"| {{NO}} |
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− | + | | RX62T ||style="text-align:center;"| {{NO}} |
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− | + | | RX630 ||style="text-align:center;"| {{NO}} |
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− | + | | RX631 ||style="text-align:center;"| {{NO}} |
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− | + | | RX63N ||style="text-align:center;"| {{NO}} |
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− | + | | RX63T ||style="text-align:center;"| {{NO}} |
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− | + | | RX64M ||style="text-align:center;"| {{NO}} |
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Latest revision as of 15:57, 20 December 2022
This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER J-Link LITE ARM V9.
Contents
Hardware Features
Feature | Supported |
---|---|
USB 2.0 Full Speed | |
JTAG interface | |
SWD interface | |
SWO interface | |
SPI interface | |
QSPI interface | |
Microchip ICSP interface | |
Renesas FINE interface | |
SiLabs C2 2-wire interface | |
ETB Trace ARM7/9 | |
ETB Trace Cortex-M | |
ETB Trace Cortex-A/R | |
ETM Trace Cortex-M | |
VCOM | |
Memory Stop mode support | |
Cortex-M Monitor Mode debugging | |
SWD Multi-Drop | |
CMSIS-DAP mode |
Supported cores
J-Link provides debugging support for the following cores.
Note:
If you are interested in J-Link support for a core that is not listed here, please feel free to request support via the SEGGER support ticket system.
If you are interested in J-Link support for a core that is not listed here, please feel free to request support via the SEGGER support ticket system.
Core | Supported |
---|---|
ARM legacy Cores | |
ARM7 | |
ARM9 | |
ARM11 | |
ARM Cortex Cores | |
Cortex-A5 | |
Cortex-A7 | |
Cortex-A8 | |
Cortex-A9 | |
Cortex-A12 | |
Cortex-A15 | |
Cortex-A17 | |
Cortex-A53 | |
Cortex-A55 | |
Cortex-A57 | |
Cortex-A72 | |
Cortex-M0 | |
Cortex-M0+ | |
Cortex-M1 | |
Cortex-M3 | |
Cortex-M4 | |
Cortex-M7 | |
Cortex-M23 | |
Cortex-M33 | |
Cortex-R4 | |
Cortex-R5 | |
Cortex-R8 | |
SC000 (M0 secure) | |
SC300 (M3 secure) | |
RISC-V | |
RV32 | |
RV64 | |
Microchip PIC32 | |
PIC32MX | |
PIC32MZ | |
SiLabs 8051 | |
EFM8 | |
Renesas RX | |
RX110 | |
RX111 | |
RX210 | |
RX21A | |
RX220 | |
RX610 | |
RX621 | |
RX62G | |
RX62G | |
RX62N | |
RX62T | |
RX630 | |
RX631 | |
RX63N | |
RX63T | |
RX64M |