Difference between revisions of "J-Trace PRO Cortex V3"
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− | This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER '''J-Trace PRO for Cortex |
+ | This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER '''J-Trace PRO for Cortex V3'''. |
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__TOC__ |
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− | == Hardware Features == |
+ | == Hardware and Software Features == |
− | {| class=" |
+ | {| class="wikitable" |
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+ | ! style="position:sticky; top:0"|Hardware version |
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− | ! Feature !! Supported |
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+ | ! style="position:sticky; top:0"|3 |
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+ | |- style="text-align:center" |
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+ | |colspan="7"| Hardware Features |
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+ | ! style="text-align:left;"|USB 2.0 Hi-Speed || {{YES}} |
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+ | ! style="text-align:left;"|USB 3.0 SuperSpeed || {{YES}} |
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− | + | ! style="text-align:left;"|WinUSB || {{YES}} |
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− | + | ! style="text-align:left;"|Gigabit-Ethernet || {{YES}} |
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− | + | ! style="text-align:left;"|cJTAG interface || {{YES}} |
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+ | ! style="text-align:left;"|cJTAG interface without/buggy KEEPER logic || {{YES}} |
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− | + | ! style="text-align:left;"|JTAG interface || {{YES}} |
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− | + | ! style="text-align:left;"|SWD interface || {{YES}} |
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− | + | ! style="text-align:left;"|SWO interface || {{YES}} |
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− | + | ! style="text-align:left;"|ETB Trace Cortex || {{YES}} |
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− | + | ! style="text-align:left;"|ETM Trace Cortex || {{YES}} |
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− | + | ! style="text-align:left;"|PTM Trace Cortex || {{YES}} |
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− | + | ! style="text-align:left;"|Streaming Trace || {{YES}} |
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− | + | ! style="text-align:left;"|VCOM || {{NO}} |
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− | + | ! style="text-align:left;"|Memory Stop mode support || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-M Monitor Mode debugging || {{YES}} |
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− | + | ! style="text-align:left;"|5 V Target Supply || {{YES}} |
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− | + | ! style="text-align:left;"|SWD Multi-Drop || {{YES}} |
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− | |} |
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− | == Supported cores == |
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− | J-Trace provides debugging support for the following cores.<br> |
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− | {{Note|1=If you are interested in J-Trace support for a core that is not listed here, please feel free to request support via the [https://www.segger.com/ticket SEGGER support ticket system].}} |
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− | {| class="seggertable" |
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− | |- |
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− | ! Core !! Supported |
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+ | ! style="text-align:left;"|CMSIS-DAP mode || {{NO}} |
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− | !colspan="2"| ARM Cortex Cores |
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+ | |- style="text-align:center" |
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+ | |colspan="7"| ARM Cortex Cores |
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− | + | ! style="text-align:left;"|Cortex-A5 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A7 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A8 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A9 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A12 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A15 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A17 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-A53 || {{NO}} |
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− | + | ! style="text-align:left;"|Cortex-A55 || {{NO}} |
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− | + | ! style="text-align:left;"|Cortex-A57 || {{NO}} |
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− | + | ! style="text-align:left;"|Cortex-A72 || {{NO}} |
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− | + | ! style="text-align:left;"|Cortex-R4 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-R5 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-R8 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-M0 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-M0+ || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-M1 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-M3 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-M4 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-M7 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-M23 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-M33 || {{YES}} |
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− | + | ! style="text-align:left;"|Cortex-M85 || {{YES}} |
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+ | ! style="text-align:left;"|SC000 (M0 secure) || {{YES}} |
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+ | ! style="text-align:left;"|SC300 (M3 secure) || {{YES}} |
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+ | |- style="text-align:center" |
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− | !colspan="2"| RISC-V |
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+ | |colspan="7"| RISC-V |
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− | + | ! style="text-align:left;"|RV32 || {{NO}} |
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− | + | ! style="text-align:left;"|RV64 || {{NO}} |
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Revision as of 16:21, 20 December 2022
This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER J-Trace PRO for Cortex V3.
Contents
Hardware and Software Features
Hardware version | 3 | |||||
---|---|---|---|---|---|---|
Hardware Features | ||||||
USB 2.0 Hi-Speed | ||||||
USB 3.0 SuperSpeed | ||||||
WinUSB | ||||||
Gigabit-Ethernet | ||||||
cJTAG interface | ||||||
cJTAG interface without/buggy KEEPER logic | ||||||
JTAG interface | ||||||
SWD interface | ||||||
SWO interface | ||||||
ETB Trace Cortex | ||||||
ETM Trace Cortex | ||||||
PTM Trace Cortex | ||||||
Streaming Trace | ||||||
VCOM | ||||||
Memory Stop mode support | ||||||
Cortex-M Monitor Mode debugging | ||||||
5 V Target Supply | ||||||
SWD Multi-Drop | ||||||
CMSIS-DAP mode | ||||||
ARM Cortex Cores | ||||||
Cortex-A5 | ||||||
Cortex-A7 | ||||||
Cortex-A8 | ||||||
Cortex-A9 | ||||||
Cortex-A12 | ||||||
Cortex-A15 | ||||||
Cortex-A17 | ||||||
Cortex-A53 | ||||||
Cortex-A55 | ||||||
Cortex-A57 | ||||||
Cortex-A72 | ||||||
Cortex-R4 | ||||||
Cortex-R5 | ||||||
Cortex-R8 | ||||||
Cortex-M0 | ||||||
Cortex-M0+ | ||||||
Cortex-M1 | ||||||
Cortex-M3 | ||||||
Cortex-M4 | ||||||
Cortex-M7 | ||||||
Cortex-M23 | ||||||
Cortex-M33 | ||||||
Cortex-M85 | ||||||
SC000 (M0 secure) | ||||||
SC300 (M3 secure) | ||||||
RISC-V | ||||||
RV32 | ||||||
RV64 |