Difference between revisions of "Microchip PIC32CM JH"

Revision as of 11:10, 14 September 2023

. The Microchip PIC32CM JH are Robust Security, Ultra-Low Power and Enhanced Touch Microcontrollers Based on Arm® Cortex®-M0 Core.

Flash Bank	Base address	Size
Internal Flash	0x00000000	256/512 KB
Data Flash	0x00400000	8 KB
User Row	0x00804000	8 B

If the watchdog is enabled, it is feed.
If watchdog is in window mode, no feeding is done, because timer registers are no accessible.

The devices access level is checked first, we need 0x02 for full access.
If devices access level is not 0x02, user is asked for protection remove by chip erase.
If CPU can be accessed, hot plugging(attach) is tried, otherwise cold plugging is executed, which puts CPU after BOOT Rom in CPU Park mode.

The devices uses normal Cortex-M reset, but special communication with BOOT Rom is done afterwards to put CPU in CPU park mode.

Attach is supported if device is not secured.
This is called hot plugging by Microchip.

@@ Line 1: / Line 1: @@
 .
-The '''Microchip PIC32CM Lx''' are Robust Security, Ultra-Low Power and Enhanced Touch Microcontrollers Based on Arm® Cortex®-M23 Core.
+The '''Microchip PIC32CM JH''' are Robust Security, Ultra-Low Power and Enhanced Touch Microcontrollers Based on Arm® Cortex®-M0 Core.
 __TOC__
@@ Line 11: / Line 11: @@
 | Internal Flash || 0x00000000 || 256/512 KB || style="text-align:center;"| {{YES}}
 |-
-| Data Flash || 0x00400000 || 8/16 KB || style="text-align:center;"| {{YES}}
+| Data Flash || 0x00400000 || 8 KB || style="text-align:center;"| {{YES}}
 |-
-| User Row || 0x00804000 || 36 B || style="text-align:center;"| {{YES}}
+| User Row || 0x00804000 || 8 B || style="text-align:center;"| {{YES}}
-|-
-| BOCOR || 0x0080C000|| 8/32/48 B || style="text-align:center;"| {{YES}}
 |}