Difference between revisions of "Microchip PIC32CM Lx"
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| + | The '''Microchip PIC32CM Lx''' are Robust Security, Ultra-Low Power and Enhanced Touch Microcontrollers Based on Arm® Cortex®-M23 Core. |
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| − | . |
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| − | The '''Microchip PIC32MC Lx''' are Robust Security, Ultra-Low Power and Enhanced Touch Microcontrollers Based on Arm® Cortex®-M0+ Core. |
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__TOC__ |
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! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
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+ | | Internal Flash || 0x00000000 || 256/512 KB || style="text-align:center;"| {{YES}} |
| − | |} |
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| − | |||
| − | ====ECC Flash [OPTIONAL]==== |
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| − | *Describe ECC Flash restriction here. |
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| − | |||
| − | ===QSPI Flash=== |
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| − | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
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| − | J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in '''bold'''. |
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| − | {| class="seggertable" |
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|- |
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| + | | Data Flash || 0x00400000 || 8/16 KB || style="text-align:center;"| {{YES}} |
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| − | ! Device !! Base address !! Maximum size !! Supported pin configuration |
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| + | | User Row || 0x00804000 || 36 B || style="text-align:center;"| {{YES}} |
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| − | | [DEVICE]|| [BANK_BASE_ADDRESS] || [MAX_SPI_FLASH_SIZE] MB || |
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| + | |- |
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| − | *'''[LOADER_NAME]''' |
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| + | | BOCOR || 0x0080C000|| 8/32/48 B || style="text-align:center;"| {{YES}} |
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| − | *[LOADER_NAME] |
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| − | *[LOADER_NAME] |
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|} |
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| − | ==ECC RAM [OPTIONAL]== |
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| − | *Describe ECC RAM restriction here. |
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| − | |||
| − | ==Vector Table Remap [OPTIONAL]== |
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| − | *Describe Vector Table Remap here.. |
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==Watchdog Handling== |
==Watchdog Handling== |
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| + | *If the watchdog is enabled, it is feed. |
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| − | *The device does not have a watchdog. |
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| + | *If watchdog is in window mode, no feeding is done, because timer registers are no accessible. |
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| − | *The device has a watchdog [WATCHDOGNAME]. |
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| − | *The watchdog is fed during flash programming. |
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| − | *If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
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| + | ==Device Specific Handling== |
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| + | ===Connect=== |
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| − | ==Multi-Core Support [OPTIONAL]== |
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| + | *The devices access level is checked first, we need 0x02 for full access.<br> |
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| − | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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| + | *If devices access level is not 0x02, user is asked for protection remove by chip erase.<br> |
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| − | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
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| + | *If CPU can be accessed, hot plugging(attach) is tried, otherwise cold plugging is executed, which puts CPU after BOOT Rom in CPU Park mode. |
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| − | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
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| − | Some of the are available with enabled ''lockstep'' mode, only. <br> |
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| − | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| − | ===Main core=== |
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| − | ====Init/Setup==== |
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| − | *Initializes the ECC RAM, see [[XXX | XXX]] |
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| − | *Enables debugging |
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| − | ====Reset==== |
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| − | *Device specific reset is performed, see [[XXX | XXX]] |
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| − | ====Attach==== |
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| − | *Attach is not supported because the J-Link initializes certain RAM regions by default |
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| − | ===Secondary core(s)=== |
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| − | ====Init/Setup==== |
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| − | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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| − | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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| − | ====Reset==== |
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| − | No reset is performed. |
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| − | ====Attach==== |
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| − | *Attach is supported / desired |
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| − | ==Device Specific Handling== |
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===Reset=== |
===Reset=== |
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| − | *The devices uses normal Cortex-M reset, |
+ | *The devices uses normal Cortex-M reset, but special communication with BOOT Rom is done afterwards to put CPU in CPU park mode. |
| − | *The devices uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
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| − | *The devices uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
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| − | *The device uses custom reset:..... |
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| − | |||
| − | ==Limitations== |
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| − | ===Dual Core Support=== |
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| − | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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===Attach=== |
===Attach=== |
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| − | Attach is |
+ | Attach is supported if device is not secured.<br> |
| + | This is called hot plugging by Microchip. |
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==Evaluation Boards== |
==Evaluation Boards== |
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| + | *Microchip PIC32CM LS60 Curiosity Pro evaluation board: [[Microchip CuriosityPro PIC32CMLS60]] |
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| − | *[SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard |
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| + | *Microchip PIC32CM LS00 Curiosity Pro evaluation board: [[Microchip CuriosityPro PIC32CMLS00]] |
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| + | *Microchip PIC32CM LE00 Curiosity Pro evaluation board: [[Microchip CuriosityPro PIC32CMLE00]] |
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==Example Application== |
==Example Application== |
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| − | * |
+ | *Microchip PIC32CM LS60 Curiosity Pro evaluation board: [[Microchip CuriosityPro PIC32CMLS60#Example_Project] |
| + | *Microchip PIC32CM LS00 Curiosity Pro evaluation board: [[Microchip CuriosityPro PIC32CMLS00#Example_Project] |
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| + | *Microchip PIC32CM LE00 Curiosity Pro evaluation board: [[Microchip CuriosityPro PIC32CMLE00#Example_Project] |
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Revision as of 11:22, 10 October 2023
The Microchip PIC32CM Lx are Robust Security, Ultra-Low Power and Enhanced Touch Microcontrollers Based on Arm® Cortex®-M23 Core.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal Flash | 0x00000000 | 256/512 KB | 
|
| Data Flash | 0x00400000 | 8/16 KB |
|
| User Row | 0x00804000 | 36 B |
|
| BOCOR | 0x0080C000 | 8/32/48 B |
|
Watchdog Handling
- If the watchdog is enabled, it is feed.
- If watchdog is in window mode, no feeding is done, because timer registers are no accessible.
Device Specific Handling
Connect
- The devices access level is checked first, we need 0x02 for full access.
- If devices access level is not 0x02, user is asked for protection remove by chip erase.
- If CPU can be accessed, hot plugging(attach) is tried, otherwise cold plugging is executed, which puts CPU after BOOT Rom in CPU Park mode.
Reset
- The devices uses normal Cortex-M reset, but special communication with BOOT Rom is done afterwards to put CPU in CPU park mode.
Attach
Attach is supported if device is not secured.
This is called hot plugging by Microchip.
Evaluation Boards
- Microchip PIC32CM LS60 Curiosity Pro evaluation board: Microchip CuriosityPro PIC32CMLS60
- Microchip PIC32CM LS00 Curiosity Pro evaluation board: Microchip CuriosityPro PIC32CMLS00
- Microchip PIC32CM LE00 Curiosity Pro evaluation board: Microchip CuriosityPro PIC32CMLE00
Example Application
- Microchip PIC32CM LS60 Curiosity Pro evaluation board: [[Microchip CuriosityPro PIC32CMLS60#Example_Project]
- Microchip PIC32CM LS00 Curiosity Pro evaluation board: [[Microchip CuriosityPro PIC32CMLS00#Example_Project]
- Microchip PIC32CM LE00 Curiosity Pro evaluation board: [[Microchip CuriosityPro PIC32CMLE00#Example_Project]
