Difference between revisions of "MindMotion MM32F5"

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(→‎Option Byte)
(→‎Internal Flash)
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! Device || StartAddr !! Size || J-Link Support
  
! Device || StartAddr !! Size || J-Link Support
 
|-
  
|-
−
| MM32F5233 ||0x08000000 || 128 KB || YES
 +
| MM32F5233 ||0x08000000 || 128 KB || {{YES}}
 
|-
  
|-
−
| MM32F5333 ||0x08000000 || 128 KB || YES
 +
| MM32F5333 ||0x08000000 || 128 KB || {{YES}}
 
|-
  
|-
−
| MM32F5277 ||0x08000000 || 256 KB || YES
 +
| MM32F5277 ||0x08000000 || 256 KB || {{YES}}
 
|-
  
|-
−
| MM32F5287 ||0x08000000 || 256 KB || YES
 +
| MM32F5287 ||0x08000000 || 256 KB || {{YES}}
 
|}
  
|}
   

Revision as of 13:30, 7 September 2023

The Mindmotion MM32F5 series microcontrollers are based on ARM®STAR-MC1 processor. Built-in
L1 ICache, DCache, instruction tightly coupled memory ITCM and data tightly coupled memory DTCM,
with high performance and low power consumption.

Supported Flash Banks

Internal Flash

Device StartAddr Size J-Link Support
MM32F5233 0x08000000 128 KB YES.png
MM32F5333 0x08000000 128 KB YES.png
MM32F5277 0x08000000 256 KB YES.png
MM32F5287 0x08000000 256 KB YES.png

QSPI flash

Device StartAddr Size J-Link Support
MM32F5277 0x90000000 External, up to 256MB YES
MM32F5287 0x90000000 In package, 1024/2048KB YES

Option Byte

Device StartAddr Size J-Link Support
MM32F5233 0x1FFFF800 512 Byte YES
MM32F5333 0x1FFFF800 512 Byte YES
MM32F5277 0x1FFFF800 512 Byte YES
MM32F5287 0x1FFFF800 512 Byte YES 
  *** Additional information ***
  • Pay attention, for debug and flash program support maximum CPU Frequency is 96 MHz.
  • After erasing the option byte on MM32F5233/MM32F5333 devices, the correct boot address has to be programmed at BOOT_ADDR.

Reset

The device uses normal reset, no special handling necessary.

Minimum requirements

  • J-Link software V7.92e or later

Evaluation Boards

Example Application

Retrieved from "https://wiki.segger.com/index.php?title=MindMotion_MM32F5&oldid=16217"