Multi-Core Debugging

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The J-Link support both approaches: SMP and AMP and of course hybrid solutions. Unfortunately, multi-core debugging is not as straight forward or as simple as it sounds. Why? Customer requirements highly depend on the actual use case and on the available multi-core debug related features provided by the chosen SoC such as individual reset functionality of the different cores. Those requirements make it difficult to provide a out-of-the-box solution, which covers all use cases. For that reason, the J-Link supports the most common use cases by default. This behavior should be well documented on the corresponding device family page. Other scenarios can be also supported but may require some custom configurations. Please feel free to get in touch with SEGGER in such cases.

Memory

There are two different approaches:

• Shared memory regions
• Exclusive memory regions

Latter one is quite simple to handle from J-Link perspective. Whereas shared memory regions are more difficult to handle due to the different requirements:

• Main core session initializes the entire shared memory region
• Main core session initializes only parts of the shared region while the second core session initialize the remaining memory
• ...

Terminologies

Basically, there are two different approaches when it comes to multi-core setups:

SMP (Symmetrical multiprocessing)

TBD

AMP (Asymmetrical multiprocessing)

TBD