Multi-Core Debugging

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Multiple cores in one SoC increases the functionality as well the performance of a single SoC. However, when it comes to debugging, multi-core SoCs are not as straight forward or as simple as they sound. Why? Customer requirements highly depend on the actual use case and on the available multi-core debug related features provided by the chosen SoC such as individual reset functionality of the different cores. Those requirements make it difficult to provide a out-of-the-box solution, which covers all use cases. For that reason, the J-Link supports the most common use cases by default. This behavior should be well documented on the corresponding device family page. Other scenarios can be also supported but may require some custom configurations. Please feel free to get in touch with SEGGER in such cases.


There are two different approaches:

  • Shared memory regions
  • Exclusive memory regions

Latter one is quite simple to handle from J-Link perspective because the main as well as the secondary core handle their dedicated memory regions, only. Compared to this, shared memory regions are more difficult to handle due to the different requirements / use cases:

  • Main core session initializes the entire shared memory region
  • Main core session initializes only parts of the shared region while the second core session initialize the remaining memory
  • ...


Not supported out-of-the-box. Please get in touch with SEGGER if support is required.


Lockstep core configurations add redundancy to the SoC by executing the same set of operations at the same time in parallel on a dedicated core. This allows to detect errors and to continue execution in case of one of the cores from the lockstep configuration crashes.


Basically, you distinguish between the different combination of cores:

  • Homogeneous (two or more copies of the same core)
  • Heterogeneous (two or more different kinds of cores)

and between how they are used:

  • SMP (Symmetrical multiprocessing)
  • AMP (Asymmetrical multiprocessing)

The J-Link supports all different combinations of the core combinations as well as of the chosen user implementation (SMP / AMP).

Multi core debugging with J-Link

Refer to The J-Link / J-Trace User Guide