Difference between revisions of "NXP NCJ29D5"
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| Normal-Domain Application || 0x00200000 || 128 KB || style="text-align:center;"| {{YES}} |
| Normal-Domain Application || 0x00200000 || 128 KB || style="text-align:center;"| {{YES}} |
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|- |
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− | | RX Radio Configurations || |
+ | | RX Radio Configurations || 0x00238A00 || 8 KB || style="text-align:center;"| {{NO}} |
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− | | TX Radio Configurations || |
+ | | TX Radio Configurations || 0x0023AA00 || 8 KB || style="text-align:center;"| {{NO}} |
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|- |
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| Customer Configuration Page || 0x0023C000 || 512 B || style="text-align:center;"| {{NO}} |
| Customer Configuration Page || 0x0023C000 || 512 B || style="text-align:center;"| {{NO}} |
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====ECC Flash==== |
====ECC Flash==== |
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*Device has ECC flash, reading of un-programmed or erased areas will result in an error. |
*Device has ECC flash, reading of un-programmed or erased areas will result in an error. |
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− | *Dedicated verify and blank check functions |
+ | *Dedicated verify and blank check functions are implemented. |
==Watchdog Handling== |
==Watchdog Handling== |
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− | *The device |
+ | *The device has a watchdog which is enabled by default after Reset with 20s timeout. |
+ | *On connect, the reset source of the watchdog will be disabled, so it keeps running, but doesn't force a reset. |
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− | *The device has a watchdog [WATCHDOGNAME]. |
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− | *The watchdog is fed during flash programming. |
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− | *If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
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− | |||
− | ==Multi-Core Support [OPTIONAL]== |
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− | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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− | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
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− | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
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− | Some of the are available with enabled ''lockstep'' mode, only. <br> |
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− | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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− | ===Main core=== |
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− | ====Init/Setup==== |
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− | *Initializes the ECC RAM, see [[XXX | XXX]] |
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− | *Enables debugging |
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− | ====Reset==== |
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− | *Device specific reset is performed, see [[XXX | XXX]] |
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====Attach==== |
====Attach==== |
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− | *Attach is |
+ | *Attach is supported. |
− | ===Secondary core(s)=== |
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− | ====Init/Setup==== |
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− | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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− | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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− | ====Reset==== |
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− | No reset is performed. |
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− | ====Attach==== |
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− | *Attach is supported / desired |
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==Device Specific Handling== |
==Device Specific Handling== |
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===Reset=== |
===Reset=== |
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− | *The devices uses normal Cortex-M reset |
+ | *The devices uses normal Cortex-M reset. |
+ | *After Reset Watchdog is disabled as described above. |
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− | *The devices uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
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− | *The devices uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
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− | *The device uses custom reset:..... |
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− | |||
− | ==Limitations== |
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− | ===Dual Core Support=== |
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− | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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− | |||
− | ===Attach=== |
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− | Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
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==Evaluation Boards== |
==Evaluation Boards== |
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+ | *NXP NCJ29D5 UWB Shield Board V4 evaluation board: [[NXP LID2435]] |
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− | *[SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard |
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==Example Application== |
==Example Application== |
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+ | *NXP NCJ29D5 UWB Shield Board V4 evaluation board: [[NXP LID2435#Example Project]] |
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− | *[SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project |
Revision as of 11:23, 10 October 2023
The NXP NCJ29D5 are Ultra-Wideband (UWB) ICs designed specifically to meet the connectivity and safety needs of the global automotive industry.
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Normal-Domain Application | 0x00200000 | 128 KB | |
RX Radio Configurations | 0x00238A00 | 8 KB | |
TX Radio Configurations | 0x0023AA00 | 8 KB | |
Customer Configuration Page | 0x0023C000 | 512 B | |
Baseband DSP Firmware | 0x00230000 | 35 KB |
ECC Flash
- Device has ECC flash, reading of un-programmed or erased areas will result in an error.
- Dedicated verify and blank check functions are implemented.
Watchdog Handling
- The device has a watchdog which is enabled by default after Reset with 20s timeout.
- On connect, the reset source of the watchdog will be disabled, so it keeps running, but doesn't force a reset.
Attach
- Attach is supported.
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset.
- After Reset Watchdog is disabled as described above.
Evaluation Boards
- NXP NCJ29D5 UWB Shield Board V4 evaluation board: NXP LID2435
Example Application
- NXP NCJ29D5 UWB Shield Board V4 evaluation board: NXP LID2435#Example Project