Difference between revisions of "NXP PN7462"
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==Watchdog Handling== |
==Watchdog Handling== |
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− | *The device |
+ | *The device has a watchdog timer [WDT]. |
+ | *The watchdog is not fed during flash programming. |
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− | *The device has a watchdog [WATCHDOGNAME]. |
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− | *The watchdog is fed during flash programming. |
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− | *If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
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− | |||
==Multi-Core Support [OPTIONAL]== |
==Multi-Core Support [OPTIONAL]== |
Revision as of 14:53, 20 September 2023
The NXP PN7462 family is a family of 32-bit Arm Cortex-M0-based NFC microcontrollers offering high performance and low power consumption.
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Internal Flash | 0x00203000 | Up to 158 KB | |
EEPROM | 0x00201200 | 3584 B |
Watchdog Handling
- The device has a watchdog timer [WDT].
- The watchdog is not fed during flash programming.
Multi-Core Support [OPTIONAL]
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The [DeviceFamily]family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core
Init/Setup
- Initializes the ECC RAM, see XXX
- Enables debugging
Reset
- Device specific reset is performed, see XXX
Attach
- Attach is not supported because the J-Link initializes certain RAM regions by default
Secondary core(s)
Init/Setup
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the secondary core is not enabled yet, it will be enabled / release from reset
Reset
No reset is performed.
Attach
- Attach is supported / desired
Device Specific Handling
Connect
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
- The devices uses Cortex-M Core reset, no special handling necessary, like described here.
- The devices uses Cortex-M Rest Pin, no special handling necessary, like described here.
- The devices uses Cortex-A reset, no special handling necessary, like described here.
- The devices uses Cortex-R reset, no special handling necessary, like described here.
- The devices uses ARMv8-A reset, no special handling necessary, like described here.
- The devices uses ARMv8-R reset, no special handling necessary, like described here.
- The device uses custom reset:.....
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
Security
Evaluation Boards
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
Example Application
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project
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