Difference between revisions of "NXP PN7462"
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| + | The '''NXP PN7462''' family is a family of 32-bit Arm Cortex-M0-based NFC microcontrollers |
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| − | The '''NXP PN7''' are [SHORT_DESCRIPTION] |
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| + | offering high performance and low power consumption. |
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__TOC__ |
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! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
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+ | | Internal Flash || 0x00203000 || Up to 158 KB || style="text-align:center;"| {{YES}} |
| − | |} |
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| − | |||
| − | ====ECC Flash [OPTIONAL]==== |
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| − | *Describe ECC Flash restriction here. |
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| − | |||
| − | ===QSPI Flash=== |
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| − | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
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| − | J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in '''bold'''. |
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| − | {| class="seggertable" |
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|- |
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| + | | EEPROM || 0x00201200|| 3584 B || style="text-align:center;"| {{YES}} |
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| − | ! Device !! Base address !! Maximum size !! Supported pin configuration |
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| − | |- |
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| − | | [DEVICE]|| [BANK_BASE_ADDRESS] || [MAX_SPI_FLASH_SIZE] MB || |
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| − | *'''[LOADER_NAME]''' |
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| − | *[LOADER_NAME] |
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| − | *[LOADER_NAME] |
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| − | ==ECC RAM [OPTIONAL]== |
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| − | *Describe ECC RAM restriction here. |
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| − | |||
| − | ==Vector Table Remap [OPTIONAL]== |
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| − | *Describe Vector Table Remap here.. |
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==Watchdog Handling== |
==Watchdog Handling== |
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| − | *The device |
+ | *The device has a watchdog timer [WDT]. |
| + | *The watchdog is not fed during flash programming. |
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| − | *The device has a watchdog [WATCHDOGNAME]. |
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| − | *The watchdog is fed during flash programming. |
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| − | *If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
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| − | ==Multi-Core Support [OPTIONAL]== |
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| − | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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| − | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
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| − | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
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| − | Some of the are available with enabled ''lockstep'' mode, only. <br> |
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| − | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| − | ===Main core=== |
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| − | ====Init/Setup==== |
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| − | *Initializes the ECC RAM, see [[XXX | XXX]] |
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| − | *Enables debugging |
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| − | ====Reset==== |
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| − | *Device specific reset is performed, see [[XXX | XXX]] |
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| − | ====Attach==== |
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| − | *Attach is not supported because the J-Link initializes certain RAM regions by default |
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| − | ===Secondary core(s)=== |
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| − | ====Init/Setup==== |
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| − | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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| − | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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| − | ====Reset==== |
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| − | No reset is performed. |
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| − | ====Attach==== |
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| − | *Attach is supported / desired |
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==Device Specific Handling== |
==Device Specific Handling== |
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| − | ===Connect=== |
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===Reset=== |
===Reset=== |
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| + | *The device uses custom reset which halts the CPU after Boot ROM execution. |
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| − | *The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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| − | *The devices uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
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| − | *The devices uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
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| − | *The devices uses Cortex-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-A devices | here]]. |
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| − | *The devices uses Cortex-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-R devices | here]]. |
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| − | *The devices uses ARMv8-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-A devices | here]]. |
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| − | *The devices uses ARMv8-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-R devices | here]]. |
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| − | *The device uses custom reset:..... |
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| − | ==Limitations== |
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| − | ===Dual Core Support=== |
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| − | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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===Attach=== |
===Attach=== |
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| − | Attach is |
+ | Attach is supported. |
| − | ===Security=== |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | * |
+ | *NXP PN640 Performance evaluation board: [[NXP PN640 Perf Board]] |
==Example Application== |
==Example Application== |
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| + | *NXP PN640 Performance evaluation board: [[NXP PN640 Perf Board#Example Project]] |
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| − | *[SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project |
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| − | > |
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Revision as of 11:24, 10 October 2023
The NXP PN7462 family is a family of 32-bit Arm Cortex-M0-based NFC microcontrollers offering high performance and low power consumption.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal Flash | 0x00203000 | Up to 158 KB | 
|
| EEPROM | 0x00201200 | 3584 B |
|
Watchdog Handling
- The device has a watchdog timer [WDT].
- The watchdog is not fed during flash programming.
Device Specific Handling
Reset
- The device uses custom reset which halts the CPU after Boot ROM execution.
Attach
Attach is supported.
Evaluation Boards
- NXP PN640 Performance evaluation board: NXP PN640 Perf Board
Example Application
- NXP PN640 Performance evaluation board: NXP PN640 Perf Board#Example Project
