NXP RW61x

The NXP RW61x are Cortex_M33 based Wireless MCUs with Integrated Radio: 1x1 Wi-Fi® 6 + Bluetooth® Low Energy 5.3.

Flash Banks

External QSPI Flash

Flash Bank	Base address	Size	J-Link Support
QSPI	0x08000000	Up to 128MB

QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | Device has only one pin configuration.

Watchdog Handling

• No Watchdog handling

Device Specific Handling=

Reset

• The devices uses normal Cortex-M reset, no special handling necessary, like described here.
• The devices uses Cortex-M Core reset, no special handling necessary, like described here.
• The devices uses Cortex-M Rest Pin, no special handling necessary, like described here.
• The devices uses Cortex-A reset, no special handling necessary, like described here.
• The devices uses Cortex-R reset, no special handling necessary, like described here.
• The devices uses ARMv8-A reset, no special handling necessary, like described here.
• The devices uses ARMv8-R reset, no special handling necessary, like described here.
• The device uses custom reset:.....

Limitations

Dual Core Support

Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.

Attach

Attach is not supported by default because the J-Link initializes certain RAM regions by default.

Evaluation Boards

• [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard

Example Application

• [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project