NXP i.MX 8
Revision as of 17:22, 21 March 2024 by Artjom.Kister (talk | contribs) (Created page with "__TOC__ The '''NXP i.MX8''' is a embedded multicore processor consisting of one Cortex-M4 and four Cortex-A53 and two Cortex-A72. == Debugging == J-Link supports debugging f...")
Contents
The NXP i.MX8 is a embedded multicore processor consisting of one Cortex-M4 and four Cortex-A53 and two Cortex-A72.
Debugging
J-Link supports debugging for the Cortex-M4. During connect the M4 is set to execute an endless loop at 0x1FFE0000 (TCML RAM) and afterwards halted.
Reset
J-Link currently does not support device reset.