Difference between revisions of "NXP i.MX 8M"
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Reset is performed by using device-specific registers, than target CPU is halted. |
Reset is performed by using device-specific registers, than target CPU is halted. |
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====Attach==== |
====Attach==== |
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| − | Attach is supported. |
+ | Attach is not supported by default because the J-Link initializes certain RAM regions. |
==Device Specific Handling== |
==Device Specific Handling== |
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===Connect=== |
===Connect=== |
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| − | After the boot stage J-Link |
+ | After the boot stage J-Link writes an "infinite loop" code to the start of the M4s TCM RAM. |
==Evaluation Boards== |
==Evaluation Boards== |
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Latest revision as of 10:28, 8 April 2024
The NXP i.MX 8M are embedded multi-core processors consisting of one Cortex-M4 and up to four Cortex-A53.
Contents
External Boot Devices
Programming of external boot media(eMMC, SDHC, QSPI/NAND Flash) is supported natively through USB Serial interface.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The i.MX 8M family comes with a variety of multi-core options listed in the following table:
| Core | J-Link Support |
|---|---|
| 4 x Cortex-A53 | 
|
| 1 x Cortex-M4F | 
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-M4 core(s)
Init/Setup
The core(s) are enabled after boot. During connect the M4 is set to execute an endless loop at 0x1FFE0000 (TCM RAM).
Reset
Reset is performed by using device-specific registers, than target CPU is halted.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions.
Device Specific Handling
Connect
After the boot stage J-Link writes an "infinite loop" code to the start of the M4s TCM RAM.
