Difference between revisions of "NXP i.MX 8X"
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| + | The '''NXP i.MX 8X''' are embedded multi-core processors consisting of one Cortex-M4, up to two Cortex-A53 and one Tensilica HiFi 4 DSP. |
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__TOC__ |
__TOC__ |
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| + | ==External Boot Devices== |
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| − | The '''NXP i.MX 8X''' is an embedded multi-core processor consisting of one Cortex-M4, four Cortex-A35. |
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| + | Programming of external boot media(eMMC, SDHC, QSPI/NAND Flash) is supported natively through USB Serial interface. |
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| − | == |
+ | ==Watchdog Handling== |
| + | System controller firmware handles watchdog during boot and programming of boot devices. |
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| − | J-Link supports debugging for the Cortex-M4. During connect the M4 is set to execute an endless loop at 0x1FFE0000 (TCML RAM) and afterwards halted. |
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| − | == |
+ | ==Multi-Core Support== |
| + | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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| − | J-Link currently does not support device reset. |
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| + | The i.MX 8X family comes with a variety of multi-core options listed in the following table:<br> |
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| + | {| class="seggertable" |
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| + | |- |
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| + | ! Core || J-Link Support |
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| + | |- |
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| + | | 4 x Cortex-A35 ||style="text-align:center;"| {{NO}} |
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| + | |- |
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| + | | 1 x Cortex-M4F ||style="text-align:center;"| {{YES}} |
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| + | |- |
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| + | | 1 x HIFI4 DSP ||style="text-align:center;"| {{NO}} |
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| + | |- |
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| + | |} |
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| + | The i.MX 8X family processors have additional cores: |
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| + | *System Controller Unit (SCU) Cortex-M4 - responsible for system initialization and boot, power and resource management, pad configuration. |
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| + | *Security Controller (SECO) Cortex-M0 - implements various security and cryptography functions. |
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| + | |||
| + | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| + | ===Cortex-A35 core(s)=== |
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| + | ====Init/Setup==== |
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| + | The core(s) are enabled by SCU after boot. |
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| + | ====Reset==== |
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| + | Core reset is performed by SCU. |
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| + | ====Attach==== |
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| + | Attach is supported. |
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| + | |||
| + | ===Cortex-M4F core(s)=== |
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| + | ====Init/Setup==== |
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| + | The core(s) are enabled by SCU after boot. |
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| + | ====Reset==== |
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| + | Core reset is performed by SCU. |
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| + | ====Attach==== |
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| + | Attach is supported. |
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| + | |||
| + | ==Device Specific Handling== |
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| + | ===Connect=== |
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| + | A boot image should contain System Controller Unit (SCU) and Security Controller (SECO) firmware images. After the boot stage J-Link can be attached to a running target. |
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| + | By default only the main A35 core is enable, the other cores can be enabled by the bootloader or operating system kernel. |
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| + | In order to have read/write accesse to system memory, MMU should be configured accordingly. |
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| + | ===Reset=== |
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| + | J-Link does not support reset of particular cores, as it is controlled by SCU. |
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| + | |||
| + | ==Evaluation Boards== |
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| + | *[[NXP_MCIMX8QXP-CPU | MCIMX8QXP-CPU]] |
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| + | |||
| + | ==Example Application== |
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| + | *[[File:NXP_MCIMX8QXP-CPU_M4_TestProject_ES_8V10.zip]] |
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Latest revision as of 16:08, 5 April 2024
The NXP i.MX 8X are embedded multi-core processors consisting of one Cortex-M4, up to two Cortex-A53 and one Tensilica HiFi 4 DSP.
Contents
External Boot Devices
Programming of external boot media(eMMC, SDHC, QSPI/NAND Flash) is supported natively through USB Serial interface.
Watchdog Handling
System controller firmware handles watchdog during boot and programming of boot devices.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The i.MX 8X family comes with a variety of multi-core options listed in the following table:
| Core | J-Link Support |
|---|---|
| 4 x Cortex-A35 | 
|
| 1 x Cortex-M4F | 
|
| 1 x HIFI4 DSP |
|
The i.MX 8X family processors have additional cores:
- System Controller Unit (SCU) Cortex-M4 - responsible for system initialization and boot, power and resource management, pad configuration.
- Security Controller (SECO) Cortex-M0 - implements various security and cryptography functions.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-A35 core(s)
Init/Setup
The core(s) are enabled by SCU after boot.
Reset
Core reset is performed by SCU.
Attach
Attach is supported.
Cortex-M4F core(s)
Init/Setup
The core(s) are enabled by SCU after boot.
Reset
Core reset is performed by SCU.
Attach
Attach is supported.
Device Specific Handling
Connect
A boot image should contain System Controller Unit (SCU) and Security Controller (SECO) firmware images. After the boot stage J-Link can be attached to a running target. By default only the main A35 core is enable, the other cores can be enabled by the bootloader or operating system kernel. In order to have read/write accesse to system memory, MMU should be configured accordingly.
Reset
J-Link does not support reset of particular cores, as it is controlled by SCU.
