Difference between revisions of "Nations N32G03x"
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| Main Flash || 0x08000000 || Up to 64 KB || style="text-align:center;"| {{YES}} |
| Main Flash || 0x08000000 || Up to 64 KB || style="text-align:center;"| {{YES}} |
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| − | |} |
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| − | ====ECC Flash [OPTIONAL]==== |
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| − | *Describe ECC Flash restriction here. |
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| − | ===QSPI Flash=== |
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| − | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
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| − | J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in '''bold'''. |
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| − | {| class="seggertable" |
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| + | | Option Byte || 0x1FFFF600|| 16 B || style="text-align:center;"| {{YES}} |
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| − | ! Device !! Base address !! Maximum size !! Supported pin configuration |
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| − | |- |
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| − | | [DEVICE]|| [BANK_BASE_ADDRESS] || [MAX_SPI_FLASH_SIZE] MB || |
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| − | *'''[LOADER_NAME]''' |
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| − | *[LOADER_NAME] |
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| − | *[LOADER_NAME] |
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| − | ==ECC RAM [OPTIONAL]== |
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| − | *Describe ECC RAM restriction here. |
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| − | |||
| − | ==Vector Table Remap [OPTIONAL]== |
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| − | *Describe Vector Table Remap here.. |
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| − | ==Multi-Core Support [OPTIONAL]== |
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| − | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]]. |
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| − | The S32K3 family comes with a variety of multi-core options. Some devices from this family feature a secondary core which is disabled after reset / by default. Some of the are available with enabled ''lockstep'' mode, only. In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| − | ===Main core=== |
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====Init/Setup==== |
====Init/Setup==== |
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*Initializes the ECC RAM, see [[XXX | XXX]] |
*Initializes the ECC RAM, see [[XXX | XXX]] |
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Revision as of 13:00, 15 February 2023
Contents
The Nations N32G032x are general-purpose microcontroller based on the Arm® Cortex®-M0 core.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main Flash | 0x08000000 | Up to 64 KB | 
|
| Option Byte | 0x1FFFF600 | 16 B |
|
Init/Setup
- Initializes the ECC RAM, see XXX
- Enables debugging
Reset
- Device specific reset is performed, see XXX
Attach
- Attach is not supported because the J-Link initializes certain RAM regions by default
Secondary core(s)
Init/Setup
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the secondary core is not enabled yet, it will be enabled / release from reset
Reset
No reset is performed.
Attach
- Attach is supported / desired
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
- The devices uses Cortex-M Core reset, no special handling necessary, like described here.
- The devices uses Cortex-M Rest Pin, no special handling necessary, like described here.
- The device uses custom reset:.....
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
Evaluation Boards
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
Example Application
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project
