Difference between revisions of "Nations N32G03x"
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! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
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| − | | Main Flash || 0x08000000 || Up to 64 KB || style="text-align:center;"| {{YES}} |
+ | | Main Flash || style="text-align:center;"| 0x08000000 || style="text-align:center;"| Up to 64 KB || style="text-align:center;"| {{YES}} |
|- |
|- |
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| − | | Option Byte || 0x1FFFF600|| 16 B || style="text-align:center;"| {{YES}} |
+ | | Option Byte || style="text-align:center;"| 0x1FFFF600|| style="text-align:center;"| 16 B || style="text-align:center;"| {{YES}} |
|} |
|} |
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| − | |||
| − | ====Init/Setup==== |
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| − | *Initializes the ECC RAM, see [[XXX | XXX]] |
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| − | *Enables debugging |
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| − | ====Reset==== |
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| − | *Device specific reset is performed, see [[XXX | XXX]] |
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| − | ====Attach==== |
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| − | *Attach is not supported because the J-Link initializes certain RAM regions by default |
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| − | ===Secondary core(s)=== |
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| − | ====Init/Setup==== |
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| − | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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| − | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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| − | ====Reset==== |
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| − | No reset is performed. |
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| − | ====Attach==== |
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| − | *Attach is supported / desired |
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| − | |||
==Device Specific Handling== |
==Device Specific Handling== |
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===Reset=== |
===Reset=== |
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*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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| − | *The devices uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
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| − | *The devices uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
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| − | *The device uses custom reset:..... |
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| − | |||
| − | ==Limitations== |
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| − | ===Dual Core Support=== |
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| − | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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| − | ===Attach=== |
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| − | Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
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==Evaluation Boards== |
==Evaluation Boards== |
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Revision as of 13:03, 15 February 2023
Contents
The Nations N32G032x are general-purpose microcontroller based on the Arm® Cortex®-M0 core.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main Flash | 0x08000000 | Up to 64 KB | 
|
| Option Byte | 0x1FFFF600 | 16 B |
|
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
Evaluation Boards
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
Example Application
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project
