ONSemi RSL15

RSL15 is a highly integrated secure Arm Cortex-M33-based Bluetooth Low Energy 5.2 wireless MCU system-on-a-chip, with flash and RAM, built-in power management, and an extensive set of peripherals.

Debug Support

J-Link supports debugging and programming of the following memory regions.

On-Chip Memory Regions for RSL15-512

The internal flash is divided into 6 different regions:

Instance Name	Size (bytes)	Memory region	Supported by J-Link
Code Flash	360448	0x00100000 - 0x00157FFF
Data Flash	163840	0x00158000 - 0x0017FFFF
Non-Volatile Record (NVR) 4	256	0x00080400 - 0x000804FF
Non-Volatile Record (NVR) 5	256	0x00080500 - 0x000805FF
Non-Volatile Record (NVR) 6	256	0x00080600 - 0x000806FF
Non-Volatile Record (NVR) 7 (Manufacturing Test)	256	0x00080700 - 0x000807FF

On-Chip Memory Regions for RSL15-284

The internal flash is divided into 6 different regions:

Instance Name	Size (bytes)	Memory region	Supported by J-Link
Code Flash	270336	0x00100000 - 0x00141FFF
Data Flash	20480	0x00158000 - 0x0015CFFF
Non-Volatile Record (NVR) 4	256	0x00080400 - 0x000804FF
Non-Volatile Record (NVR) 5	256	0x00080500 - 0x000805FF
Non-Volatile Record (NVR) 6	256	0x00080600 - 0x000806FF
Non-Volatile Record (NVR) 7 (Manufacturing Test)	256	0x00080700 - 0x000807FF

ROM Bootloader

The RSL15 comes with a bootloader in ROM. More information on ROM bootloaders in general can be found here: ROM Bootloader.
For a documentation of the RSL15 boot sequence, refer to the RSL15 documentation.

When working with the RSL15, the following must be considered in regard to its ROM bootloader:

• Different boot modes aka. boot configurations are supported.
  • BOOT_FLASH_XTAL_DISABLE: The CM33 executes code from the flash and the XTAL will not be started at boot
    • This is the factory default for virgin RSL15 chips.
  • BOOT_CUSTOM: The CM33 executes code from the address specified in the wakeup information in retention RAM and the XTAL will not be started at boot
  • BOOT_FLASH_XTAL_DEFAULT_TRIM: The CM33 executes code from the flash and the XTAL will be started at boot with the default trim
  • BOOT_FLASH_XTAL_CUSTOM_TRIM: The CM33 executes code from the flash and the XTAL will be started at boot with trim from ACS_WAKEUP_GP_DATA
  • As of V7.82 of the J-Link software, only the BOOT_FLASH_XTAL_DISABLE boot configuration is supported by J-Link.

• The ROM BTL checks for a valid application in flash before jumping to any user code:
  • The application’s vector table must be aligned to a 512-byte boundary in memory, for a device with the number of external interrupts that are included in the RSL15 SoC.
  • The initial stack pointer must point to a valid memory location on the system bus. This requires that the specified stack pointer is 32-bit aligned, and that the next address stack data will be placed at is in DRAM or BB_DRAM.
  • The reset handler must be located immediately after the vector table (or after a CRC located after the vector table). This check is performed indirectly by confirming that the reset vector points to a location that:
    • Provides space for at least the minimum number of entries in the vector table (a minimum valid vector table contains 4 entries: the stack pointer, reset vector, NMI handler, and hard fault handler)
    • Provides space for no more than the stack pointer, the 88 potential vectors, and a CRC (maximum of 90 words between the base of the application and the reset vector’s location)

If the user application loaded into flash does not fulfill the above requirements, the ROM BTL will deem it invalid and it will not jump to the application.
The example project mentioned below may be used as a reference for a working valid application for the RSL15.

Evaluation Boards

• ONSemi RSL15-EVB: https://wiki.segger.com/ONSemi_RSL15-EVB

Example Application

• ONSemi RSL15-EVB: https://wiki.segger.com/ONSemi_RSL15-EVB#Example_Project