PSoC 4xxx series

This page contains information about the Infineon PSoC 4xxx series.

Connection behavior

The connect sequence of PSoC 4 devices is very time critical and is performed from the J-Link's side directly.

A locked PSoC 4 device is automatically set to open if it was in protected state. If the device was unlocked, the internal memory is again in erased state.

Readout protection

The following section explains how to set Infineon PSoC 4 devices in protected state and how to unprotect them.

Protection levels

For Infineon PSoC4 devices three levels of protection can be set by altering the SYSARG chip protection step in the examples above.

Value	Meaning
0x0001E0B6	Read protection level open. Device is unprotected
0x0002E0B6	Read protection level protected. Device is protected. Setting the mode to open again causes a mass erase.
0x0004E0B6	Read protection level kill. Device is protected. The protection level cannot be changed anymore. Setting to kill mode is permanent and makes the device unrecoverable.

Securing the device - pseudo code

//
// Addresses
//
if (PSOC4000) {                   // PSOC4000: CPUSS base is 0x4010_0000
  CPUSS_BASE              = 0x40100000;
} else {                          // Other:    CPUSS base is 0x4000_0000
  CPUSS_BASE              = 0x40000000;
}
CPUSS_SYSREQ              = CPUSS_BASE + 0x04;
CPUSS_SYSARG              = CPUSS_BASE + 0x08;
//
// Register bits
//
CPUSS_SYSREQ_BIT          = (1 << 31);
CPUSS_CMD_SHIFT           = 0;
//
// SROM constants
//
SROM_KEY1                 = 0xB6;
SROM_KEY2                 = 0xD3;
//
// SROM requests
//
SROM_CMD_WRITE_PROTECTION = 0x0D; // Write chip-level (and flash) protection.
SROM_CMD_SET_IMO_48MHz    = 0x15; // Set clock to 48 MHz (req. for flash programming)
//
// Chip protection levels
//
CHIP_PROT_OPEN            = 0x01; // OPEN (unprotected)
CHIP_PROT_PROTECTED       = 0x02; // PROTECTED (chip protected, reversible)
CHIP_PROT_KILL            = 0x04; // KILL (chip protected, irreversible)
//
// Protection sequence
//
if (RequiresIMO48Mhz) {
  CmdAndKey    = SROM_KEY2 + SROM_CMD_SET_IMO_48MHz;
  Params       = (SROM_KEY1 << 0)     // SROM command key 1
               | (CmdAndKey << 8)     // SROM command key 2 + Command
               ;
  CPUSS_SYSARG = Params;
  CPUSS_SYSREQ = CPUSS_SYSREQ_BIT
               | SROM_CMD_SET_IMO_48MHz
               ;
}
CmdAndKey    = SROM_KEY2 + SROM_CMD_WRITE_PROTECTION;
Params       = (SROM_KEY1 << 0)       // SROM command key 1
             | (CmdAndKey << 8)       // SROM command key 2 + Command (See: CHIP_PROT_*)
             | (ChipProtLevel << 16)  // Chip Protection level to be set
             | (0 << 24)              // Flash macro (always 0 for chip protection)
             ;
CPUSS_SYSARG = Params;
CPUSS_SYSREQ = CPUSS_SYSREQ_BIT
             | SROM_CMD_WRITE_PROTECTION
             ;

Securing device after programming

The Infineon CY8C4xxx and CYBLExxxx series devices provide chip-level protection which allows "permanent" protection of the device concerning read and write access. The sequence, to secure the device consists of multiple read / write accesses to special function registers of the CY8C4xxx and CYBLExxxx series devices.

Via J-Flash / Flasher ARM

The sequence to secure the device, needs to be added to the exit-steps of the J-Flash project. The exit steps will be executed at the end of an successful auto-programming process (Target -> Auto). J-Flash comes with an example project for the Infineon CYBLE-214009-00 device which contains a secure device programming sequence (File:Cypress CYBLE 214009-00.jflash). This sequence applies for all Infineon CY8C4xxx and CYBLExxxx series devices since they are compatible regarding secure procedure and can be adapted to fit custom requirements, by re-selecting the required device within the J-Flash project.

Note:

• PSoC4100/4200 target devices use different addresses for the SYSREQ and SYSARG registers. They are located at 0x40000004 and 0x40000008 instead. For more information please consult the Infineon Programming Specifications user guide.
• The clock of some PSoC4 target devices must be set to 48MHz before calling the locking/unlocking sequence. This can be achieved by using the "Configure Clock" Command.

Unsecuring device before reprogramming

The Infineon CY8C4xxx and CYBLExxxx series devices provide chip-level protection which allows "permanent" protection of the device concerning read and write access. The sequence, to unsecure the device consists of multiple read / write accesses to special function registers of the Infineon CY8C4xxx and CYBLExxxx series devices MCU.

Via J-Flash / Flasher ARM

J-Flash(v6.31k and following) detects if the device is secured. In case of a secured device it will unsecure it. This sequence applies for all Infineon CY8C4xxx and CYBLExxxx series devices since they are compatible regarding secure procedure.