Latest revision as of 10:19, 17 June 2020

QSPI Flash Programming Support

QSPI Flash programming support is provided through the following pin configs:

For the Renesas RZ A1H series device the following port pins are used to interface the (Q)SPI flash at channel 0 for single SPI:

For the Renesas RZ A1H series device the following port pins are used to interface the (Q)SPI flash at channel 1 are for dual SPI:

TBD.

@@ Line 1: / Line 1: @@
 __TOC__
-The NXP RZ/A1H is a high-end 32-bit CPU, based on the Cortex-A9 core.
+The Renesas RZ/A1H is a high-end 32-bit CPU, based on the Cortex-A9 core.
+= QSPI Flash Programming Support =
+QSPI Flash programming support is provided through the following pin configs:
+====Quad-SPI Interface Pins====
+For the Renesas RZ A1H series device the following port pins are used to interface the (Q)SPI flash at channel 0 for single SPI:
+{| class="wikitable"
+|-
+! Alternate function !! Port / Pin
+|-
+| SPBCLK_0           || P9_2
+|-
+| SPBSSL_0           || P9_3
+|-
+| SPIO00             || P9_4
+|-
+| SPIO10             || P9_5
+|-
+| SPIO20             || P9_6
+|-
+| SPIO30             || P9_7
+|}
+For the Renesas RZ A1H series device the following port pins are used to interface the (Q)SPI flash at channel 1 are for dual SPI:
+{| class="wikitable"
+|-
+! Alternate function !! Port / Pin
+|-
+| SPIO01             || P2_12
+|-
+| SPIO11             || P2_13
+|-
+| SPIO21             || P2_14
+|-
+| SPIO31             || P2_15
+|}
 = Programming external parallel CFI NOR flash =
 TBD.