Difference between revisions of "RZ A1L"
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__TOC__ |
__TOC__ |
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The Renesas RZ/A1L is a high-end 32-bit CPU, based on the Cortex-A9 core. |
The Renesas RZ/A1L is a high-end 32-bit CPU, based on the Cortex-A9 core. |
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− | = QSPI Flash Programming Support = |
+ | == QSPI Flash Programming Support == |
QSPI Flash programming support is provided through the following pin configs: |
QSPI Flash programming support is provided through the following pin configs: |
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− | ====Quad-SPI Interface Pins==== |
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For the Renesas RZ A1L series device the following port pins are used to interface the (Q)SPI flash at channel 1 are for dual SPI: |
For the Renesas RZ A1L series device the following port pins are used to interface the (Q)SPI flash at channel 1 are for dual SPI: |
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− | = Programming external parallel CFI NOR flash = |
+ | == Programming external parallel CFI NOR flash == |
TBD. |
TBD. |
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+ | == Tracing on Renesas RZ/A1L == |
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− | <references/> |
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+ | This section describes how to get started with trace on the Renesas RZ/A1L MCUs. |
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+ | This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). |
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+ | If this is not the case, we recommend to read '''Trace''' chapter in the J-Link User Manual (UM08001). |
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+ | {{Note|1= |
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+ | * The sample projects come with a pre-configured project file for Ozone that runs out-of-the box. |
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+ | * The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace. |
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+ | * In order to rebuild the sample project, [https://www.segger.com/embedded-studio.html SEGGER Embedded Studio] can be used. |
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+ | }} |
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+ | |||
+ | === Tracing on Renesas RZ/A1LU === |
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+ | ==== Minimum requirements ==== |
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+ | In order to use trace on the Renesas RZ/A1LU devices, the following minimum requirements have to be met: |
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+ | * J-Link software version V7.94c or later |
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+ | * Ozone V3.30d or later (if streaming trace and / or the sample project from below shall be used) |
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+ | * J-Trace PRO for Cortex-M HW version V3.0 or later for streaming trace |
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+ | * J-Link Plus V12 or later for TMC/ETB trace |
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+ | To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary. |
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+ | ==== Streaming trace ==== |
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+ | The project below has been tested with the minimum requirements mentioned above and a trace capable eval board. |
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+ | *'''Example project:''' [[Media:Renesas_RZ_A1L_TracePins.zip | Renesas_RZ_A1L_TracePins.zip]] |
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+ | ==== Trace buffer (TMC/ETB) ==== |
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+ | The project below is utilizing the on-chip trace buffer (it is '''not''' meant for streaming trace). |
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+ | *'''Example Project:''' [[Media:Renesas_RZ_A1L_TraceBuffer.zip | Renesas_RZ_A1L_TraceBuffer.zip]] |
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+ | ==== Tested Hardware ==== |
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+ | The example projects were tested with an unreleased eval board from Renesas but should work with any board design. In case of the trace pin example the trace pins mentioned in the devices reference manual need to be used. |
Latest revision as of 13:29, 15 May 2024
Contents
The Renesas RZ/A1L is a high-end 32-bit CPU, based on the Cortex-A9 core.
QSPI Flash Programming Support
QSPI Flash programming support is provided through the following pin configs:
Quad-SPI Interface Pins
For the Renesas RZ A1L series device the following port pins are used to interface the (Q)SPI flash at channel 0 for single SPI:
Alternate function | Port / Pin |
---|---|
SPBCLK_0 | P4_4 |
SPBSSL_0 | P4_5 |
SPIO00 | P4_6 |
SPIO10 | P4_7 |
SPIO20 | P4_2 |
SPIO30 | P4_3 |
For the Renesas RZ A1L series device the following port pins are used to interface the (Q)SPI flash at channel 1 are for dual SPI:
Alternate function | Port / Pin |
---|---|
SPIO01 | P3_10 |
SPIO11 | P3_11 |
SPIO21 | P3_12 |
SPIO31 | P3_13 |
Programming external parallel CFI NOR flash
TBD.
Tracing on Renesas RZ/A1L
This section describes how to get started with trace on the Renesas RZ/A1L MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).
- The sample projects come with a pre-configured project file for Ozone that runs out-of-the box.
- The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace.
- In order to rebuild the sample project, SEGGER Embedded Studio can be used.
Tracing on Renesas RZ/A1LU
Minimum requirements
In order to use trace on the Renesas RZ/A1LU devices, the following minimum requirements have to be met:
- J-Link software version V7.94c or later
- Ozone V3.30d or later (if streaming trace and / or the sample project from below shall be used)
- J-Trace PRO for Cortex-M HW version V3.0 or later for streaming trace
- J-Link Plus V12 or later for TMC/ETB trace
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
Streaming trace
The project below has been tested with the minimum requirements mentioned above and a trace capable eval board.
- Example project: Renesas_RZ_A1L_TracePins.zip
Trace buffer (TMC/ETB)
The project below is utilizing the on-chip trace buffer (it is not meant for streaming trace).
- Example Project: Renesas_RZ_A1L_TraceBuffer.zip
Tested Hardware
The example projects were tested with an unreleased eval board from Renesas but should work with any board design. In case of the trace pin example the trace pins mentioned in the devices reference manual need to be used.