Difference between revisions of "ST SR6G7"
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==ECC RAM == |
==ECC RAM == |
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Device has ECC RAM, init before first use is necessary. |
Device has ECC RAM, init before first use is necessary. |
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+ | |||
− | <!-- |
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==Multi-Core Support [OPTIONAL]== |
==Multi-Core Support [OPTIONAL]== |
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Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]]. |
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]]. |
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− | The |
+ | The SR6G7 family comes with 6 Corext-R52 and 3 Cortex-M4 cores. Some of them are available with enabled ''lockstep'' mode, only. |
+ | Please refer to the reference manual. |
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− | ===Main core=== |
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+ | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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+ | ===Cluster 0 core 0 (Cortex-R52)=== |
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====Init/Setup==== |
====Init/Setup==== |
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*Initializes the ECC RAM, see [[XXX | XXX]] |
*Initializes the ECC RAM, see [[XXX | XXX]] |
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====Init/Setup==== |
====Init/Setup==== |
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*If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
*If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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− | *If the |
+ | *If the Cluster core 1 is not enabled yet, it will be enabled / release from reset |
====Reset==== |
====Reset==== |
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No reset is performed. |
No reset is performed. |
Revision as of 16:36, 28 April 2023
Contents
The ST SR6G7xx are Stellar G series microcontroller, which inlcude 6 Cortex-R52+ and 3 Cortex-M4.
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
RWW Partition 0 | 0x28000000 | 1792 KB | |
RWW Partition 1 | 0x281C0000 | 2048 KB | |
RWW Partition 2 | 0x28400000 | 1792 KB | |
RWW Partition 3 | 0x285C0000 | 2048 KB | |
RWW Partition 4 | 0x28800000 | 2048 KB | |
RWW Partition 5 | 0x28A00000 | 2048 KB | |
RWW Partition 6 | 0x28C00000 | 2048 KB | |
RWW Partition 7 | 0x28E00000 | 2048 KB | |
RWW Partition 8 | 0x29000000 | 2048 KB | |
RWW Partition 9 | 0x29400000 | 2048 KB | |
EEPROM / RWW 10 | 0x29E00000 | 512 KB | |
UTEST / RWW 1 | 0x29F80000 | 32 KB | |
Boot Code Sector / RWW 1 | 0x29FB8000 | 16 KB | |
HSM Code / RWW 11/12 | 0x00000000 | 512 KB | |
HSM Data / RWW 13 | 0x003A0000 | 128 KB | |
HSM UT / RWW 13 | 0x0037C000 | 16 KB |
ECC Flash
Device has ECC Flash, but no special init necessary. Please refer to the reference Manual.
ECC RAM
Device has ECC RAM, init before first use is necessary.
Multi-Core Support [OPTIONAL]
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here. The SR6G7 family comes with 6 Corext-R52 and 3 Cortex-M4 cores. Some of them are available with enabled lockstep mode, only. Please refer to the reference manual. In below, the debug related multi-core behavior of the J-Link is described for each core:
Cluster 0 core 0 (Cortex-R52)
Init/Setup
- Initializes the ECC RAM, see XXX
- Enables debugging
Reset
- Device specific reset is performed, see XXX
Attach
- Attach is not supported because the J-Link initializes certain RAM regions by default
Secondary core(s)
Init/Setup
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the Cluster core 1 is not enabled yet, it will be enabled / release from reset
Reset
No reset is performed.
Attach
- Attach is supported / desired
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
- The devices uses Cortex-M Core reset, no special handling necessary, like described here.
- The devices uses Cortex-M Rest Pin, no special handling necessary, like described here.
- The device uses custom reset:.....
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
Evaluation Boards
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
Example Application
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project
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