ST SR6G7
Contents
- 1 Flash Banks
- 2 ECC RAM
- 3 Multi-Core Support [OPTIONAL]
- 4 Device Specific Handling
- 5 Limitations
- 6 Evaluation Boards
- 7 Example Application
The ST SR6G7xx are Stellar G series microcontroller, which inlcude 6 Cortex-R52+ and 3 Cortex-M4.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| RWW Partition 0 | 0x28000000 | 1792 KB | 
|
| RWW Partition 1 | 0x281C0000 | 2048 KB |
|
| RWW Partition 2 | 0x28400000 | 1792 KB |
|
| RWW Partition 3 | 0x285C0000 | 2048 KB |
|
| RWW Partition 4 | 0x28800000 | 2048 KB |
|
| RWW Partition 5 | 0x28A00000 | 2048 KB |
|
| RWW Partition 6 | 0x28C00000 | 2048 KB |
|
| RWW Partition 7 | 0x28E00000 | 2048 KB |
|
| RWW Partition 8 | 0x29000000 | 2048 KB |
|
| RWW Partition 9 | 0x29400000 | 2048 KB |
|
| EEPROM / RWW 10 | 0x29E00000 | 512 KB |
|
| UTEST / RWW 1 | 0x29F80000 | 32 KB |
|
| Boot Code Sector / RWW 1 | 0x29FB8000 | 16 KB |
|
| HSM Code / RWW 11/12 | 0x00000000 | 512 KB | 
|
| HSM Data / RWW 13 | 0x003A0000 | 128 KB |
|
| HSM UT / RWW 13 | 0x0037C000 | 16 KB |
|
ECC Flash
Device has ECC Flash, but no special init necessary. Please refer to the reference Manual.
ECC RAM
Device has ECC RAM, init before first use is necessary.
Multi-Core Support [OPTIONAL]
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The SR6G7 family comes with 6 Corext-R52 and 3 Cortex-M4 cores. Some of them are available with enabled lockstep mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-R52 Cluster 0 Core 0
Init/Setup
- Functional Reset is initiated for Cut 1.0 silicon.
- WDT is disabled
Reset
- Cortex-R reset is performed, see here
- Functional Reset is initiated for Cut 1.0 silicon.
- Initializes the 64KB ECC RAM starting at 0x60000000
- WDT is disabled
Attach
- Attach is supported, user has to take care about ECC RAM initialisation.
Cortex-R52 Cluster 0 Core 1
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- Cortex-R reset is performed, see here
Attach
- Attach is supported
Cortex-R52 Cluster 1 Core 0
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- Cortex-R reset is performed, see here
Attach
- Attach is supported
Cortex-R52 Cluster 1 Core 1
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- Cortex-R reset is performed, see here
Attach
- Attach is supported
Cortex-R52 Cluster 2 Core 0
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- Cortex-R reset is performed, see here
Attach
- Attach is supported
Secondary core(s)
Init/Setup
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the Cluster core 1 is not enabled yet, it will be enabled / release from reset
Reset
No reset is performed.
Attach
- Attach is supported
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
- The devices uses Cortex-M Core reset, no special handling necessary, like described here.
- The devices uses Cortex-M Rest Pin, no special handling necessary, like described here.
- The device uses custom reset:.....
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
Evaluation Boards
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
Example Application
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project
--!>
