Difference between revisions of "ST SR6P6"
Line 36: | Line 36: | ||
|} |
|} |
||
− | ====ECC Flash |
+ | ====ECC Flash ==== |
− | + | Device has ECC Flash, but no special init necessary. |
|
+ | Please refer to the reference Manual. |
||
− | == |
+ | ==ECC RAM == |
+ | Device has ECC RAM, init before first use is necessary. |
||
− | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
||
− | J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in '''bold'''. |
||
− | {| class="seggertable" |
||
− | |- |
||
− | ! Device !! Base address !! Maximum size !! Supported pin configuration |
||
− | |- |
||
− | | [DEVICE]|| [BANK_BASE_ADDRESS] || [MAX_SPI_FLASH_SIZE] MB || |
||
− | *'''[LOADER_NAME]''' |
||
− | *[LOADER_NAME] |
||
− | *[LOADER_NAME] |
||
− | |} |
||
− | |||
− | ==ECC RAM [OPTIONAL]== |
||
− | *Describe ECC RAM restriction here. |
||
− | |||
− | ==Vector Table Remap [OPTIONAL]== |
||
− | *Describe Vector Table Remap here.. |
||
==Multi-Core Support [OPTIONAL]== |
==Multi-Core Support [OPTIONAL]== |
Revision as of 16:54, 15 February 2023
Contents
The ST SR6P6xx are Stellar P series microcontroler, which inlcudes 6 Cortex-R52+ and 3 Cortex-M4.
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Internal program flash | 0x28000000 | 1792 KB | |
Internal program flash | 0x281C0000 | 2048 KB | |
Internal program flash | 0x28400000 | 1792 KB | |
Internal program flash | 0x285C0000 | 2048 KB | |
Internal program flash | 0x28800000 | 2048 KB | |
Internal program flash | 0x28C00000 | 2048 KB | |
Internal program flash | 0x29000000 | 2048 KB | |
Internal program flash | 0x29400000 | 2048 KB | |
EEPROM | 0x29E00000 | 512 KB | |
UTEST | 0x29F80000 | 32 KB | |
Boot Code Sector | 0x29FB8000 | 16 KB | |
HSM Code | 0x00000000 | 512 KB | |
HSM Data | 0x003A0000 | 128 KB | |
HSM UT | 0x0037C000 | 16 KB |
ECC Flash
Device has ECC Flash, but no special init necessary. Please refer to the reference Manual.
ECC RAM
Device has ECC RAM, init before first use is necessary.
Multi-Core Support [OPTIONAL]
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here. The S32K3 family comes with a variety of multi-core options. Some devices from this family feature a secondary core which is disabled after reset / by default. Some of the are available with enabled lockstep mode, only. In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core
Init/Setup
- Initializes the ECC RAM, see XXX
- Enables debugging
Reset
- Device specific reset is performed, see XXX
Attach
- Attach is not supported because the J-Link initializes certain RAM regions by default
Secondary core(s)
Init/Setup
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the secondary core is not enabled yet, it will be enabled / release from reset
Reset
No reset is performed.
Attach
- Attach is supported / desired
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
- The devices uses Cortex-M Core reset, no special handling necessary, like described here.
- The devices uses Cortex-M Rest Pin, no special handling necessary, like described here.
- The device uses custom reset:.....
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
Evaluation Boards
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
Example Application
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project