Difference between revisions of "ST SR6P6"
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==ECC RAM == |
==ECC RAM == |
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Device has ECC RAM, init before first use is necessary. |
Device has ECC RAM, init before first use is necessary. |
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==Multi-Core Support [OPTIONAL]== |
==Multi-Core Support [OPTIONAL]== |
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Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]]. |
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]]. |
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==Example Application== |
==Example Application== |
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*[SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project |
*[SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project |
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Revision as of 09:04, 20 February 2023
The ST SR6P6xx are Stellar P series microcontroler, which inlcudes 6 Cortex-R52+ and 3 Cortex-M4.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal program flash | 0x28000000 | 1792 KB | 
|
| Internal program flash | 0x281C0000 | 2048 KB |
|
| Internal program flash | 0x28400000 | 1792 KB |
|
| Internal program flash | 0x285C0000 | 2048 KB |
|
| Internal program flash | 0x28800000 | 2048 KB |
|
| Internal program flash | 0x28C00000 | 2048 KB |
|
| Internal program flash | 0x29000000 | 2048 KB |
|
| Internal program flash | 0x29400000 | 2048 KB |
|
| EEPROM | 0x29E00000 | 512 KB |
|
| UTEST | 0x29F80000 | 32 KB |
|
| Boot Code Sector | 0x29FB8000 | 16 KB |
|
| HSM Code | 0x00000000 | 512 KB | 
|
| HSM Data | 0x003A0000 | 128 KB |
|
| HSM UT | 0x0037C000 | 16 KB |
|
ECC Flash
Device has ECC Flash, but no special init necessary. Please refer to the reference Manual.
ECC RAM
Device has ECC RAM, init before first use is necessary.
