Difference between revisions of "ST SR6P6"

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==ECC RAM ==
  
==ECC RAM ==
 
Device has ECC RAM, init before first use is necessary.
  
Device has ECC RAM, init before first use is necessary.
  +
−
<!--
  
 
==Multi-Core Support [OPTIONAL]==
  
==Multi-Core Support [OPTIONAL]==
−
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].
 +
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br>
−
The S32K3 family comes with a variety of multi-core options. Some devices from this family feature a secondary core which is disabled after reset / by default. Some of the are available with enabled ''lockstep'' mode, only. In below, the debug related multi-core behavior of the J-Link is described for each core:
 +
The SR6G7 family comes with 6 Corext-R52 and 3 Cortex-M4 cores. Some of them are available with enabled ''lockstep'' mode, only.<br>
  +
Please refer to the reference manual. <br>
−
===Main core===
  
  +
In below, the debug related multi-core behavior of the J-Link is described for each core:<br>
  +
===Cortex-R52 Cluster 0 Core 0 ===
 
====Init/Setup====
  
====Init/Setup====
  +
*Functional Reset is initiated for Cut 1.0 silicon.
−
*Initializes the ECC RAM, see [[XXX | XXX]]
  
  +
*WDT is disabled
−
*Enables debugging
  
 
====Reset====
  
====Reset====
−
*Device specific reset is performed, see [[XXX | XXX]]
 +
*Cortex-R Reset Pin is performed
  +
*Functional Reset is initiated for Cut 1.0 silicon.
  +
*Initializes the 64KB ECC RAM starting at 0x60000000
  +
*WDT is disabled
 
====Attach====
  
====Attach====
−
*Attach is not supported because the J-Link initializes certain RAM regions by default
 +
*Attach is supported, user has to take care about ECC RAM initialisation.
  +
−
===Secondary core(s)===
  
  +
===Cortex-R52 Cluster 0 Core 1 ===
 
====Init/Setup====
  
====Init/Setup====
  +
*WDT is disabled
−
*If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
  
−
*If the secondary core is not enabled yet, it will be enabled / release from reset
 +
*If core is not enabled, it will be enabled (set to DRUN condition).
 
====Reset====
  
====Reset====
−
No reset is performed.
 +
*Cortex-R Reset Pin is performed
 
====Attach====
  
====Attach====
−
*Attach is supported / desired
 +
*Attach is supported
   
  +
===Cortex-R52 Cluster 1 Core 0 ===
−
==Device Specific Handling==
  
−
===Reset===
 +
====Init/Setup====
  +
*WDT is disabled
−
*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]].
  
  +
*If core is not enabled, it will be enabled (set to DRUN condition).
−
*The devices uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]].
  
  +
====Reset====
−
*The devices uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]].
  
  +
*Cortex-R Reset Pin is performed
−
*The device uses custom reset:.....
  
  +
====Attach====
  +
*Attach is supported
   
  +
===Cortex-R52 Cluster 1 Core 1 ===
−
==Limitations==
  
−
===Dual Core Support===
 +
====Init/Setup====
  +
*WDT is disabled
−
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
  
  +
*If core is not enabled, it will be enabled (set to DRUN condition).
  +
====Reset====
  +
*Cortex-R Reset Pin is performed
  +
====Attach====
  +
*Attach is supported
   
  +
===Cortex-R52 Cluster 2 Core 0 ===
−
===Attach===
  
  +
====Init/Setup====
−
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
  
  +
*WDT is disabled
  +
*If core is not enabled, it will be enabled (set to DRUN condition).
  +
====Reset====
  +
*Cortex-R Reset Pin is performed
  +
====Attach====
  +
*Attach is supported
   
−
==Evaluation Boards==
 +
===DSPH Core ===
  +
====Init/Setup====
−
*[SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
  
  +
*
  +
====Reset====
  +
*Cortex-R Reset Pin is performed
  +
====Attach====
  +
*Attach is supported
   
  +
−
==Example Application==
  
  +
==Device Specific Handling==
−
*[SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project
  
  +
===Reset===
−
--!>
  
  +
*The devices uses Cortex-AR Reset Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal_3 | here]].
  +
==Evaluation Boards==
  +
*ST SR6G7-EVB60000P evaluation board: http://wiki.segger.local/SR6G7-EVB60000P

Revision as of 17:21, 28 April 2023

The ST SR6P6xx are Stellar P series microcontroler, which inlcudes 6 Cortex-R52+ and 3 Cortex-M4.

Flash Banks

Internal Flash

Flash Bank Base address Size J-Link Support
RWW Partition 0 0x28000000 1792 KB YES.png
RWW Partition 1 0x281C0000 2048 KB YES.png
RWW Partition 2 0x28400000 1792 KB YES.png
RWW Partition 3 0x285C0000 2048 KB YES.png
RWW Partition 4 0x28800000 2048 KB YES.png
RWW Partition 5 0x28C00000 2048 KB YES.png
RWW Partition 6 0x29000000 2048 KB YES.png
RWW Partition 7 0x29400000 2048 KB YES.png
EEPROM / RWW 8 0x29E00000 512 KB YES.png
UTEST / RWW 1 0x29F80000 32 KB YES.png
Boot Code Sector / RWW 1 0x29FB8000 16 KB YES.png
HSM Code / RWW 9/10 0x00000000 512 KB NO.png
HSM Data / RWW 11 0x003A0000 128 KB NO.png
HSM UT / RWW 11 0x0037C000 16 KB NO.png

ECC Flash

Device has ECC Flash, but no special init necessary. Please refer to the reference Manual.

ECC RAM

Device has ECC RAM, init before first use is necessary.

Multi-Core Support [OPTIONAL]

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The SR6G7 family comes with 6 Corext-R52 and 3 Cortex-M4 cores. Some of them are available with enabled lockstep mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:

Cortex-R52 Cluster 0 Core 0

Init/Setup

  • Functional Reset is initiated for Cut 1.0 silicon.
  • WDT is disabled

Reset

  • Cortex-R Reset Pin is performed
  • Functional Reset is initiated for Cut 1.0 silicon.
  • Initializes the 64KB ECC RAM starting at 0x60000000
  • WDT is disabled

Attach

  • Attach is supported, user has to take care about ECC RAM initialisation.

Cortex-R52 Cluster 0 Core 1

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • Cortex-R Reset Pin is performed

Attach

  • Attach is supported

Cortex-R52 Cluster 1 Core 0

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • Cortex-R Reset Pin is performed

Attach

  • Attach is supported

Cortex-R52 Cluster 1 Core 1

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • Cortex-R Reset Pin is performed

Attach

  • Attach is supported

Cortex-R52 Cluster 2 Core 0

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • Cortex-R Reset Pin is performed

Attach

  • Attach is supported

DSPH Core

Init/Setup

Reset

  • Cortex-R Reset Pin is performed

Attach

  • Attach is supported


Device Specific Handling

Reset

  • The devices uses Cortex-AR Reset Pin, no special handling necessary, like described here.

Evaluation Boards

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