Difference between revisions of "ST SR6P6"
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==Multi-Core Support [OPTIONAL]== |
==Multi-Core Support [OPTIONAL]== |
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Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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| − | The |
+ | The SR6P6 family comes with 6 Corext-R52 and 3 Cortex-M4 cores. Some of them are available with enabled ''lockstep'' mode, only.<br> |
Please refer to the reference manual. <br> |
Please refer to the reference manual. <br> |
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In below, the debug related multi-core behavior of the J-Link is described for each core:<br> |
In below, the debug related multi-core behavior of the J-Link is described for each core:<br> |
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Revision as of 12:15, 9 June 2023
Contents
The ST SR6P6xx are Stellar P series microcontroler, which inlcudes 6 Cortex-R52+ and 3 Cortex-M4.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| RWW Partition 0 | 0x28000000 | 1792 KB | 
|
| RWW Partition 1 | 0x281C0000 | 2048 KB |
|
| RWW Partition 2 | 0x28400000 | 1792 KB |
|
| RWW Partition 3 | 0x285C0000 | 2048 KB |
|
| RWW Partition 4 | 0x28800000 | 2048 KB |
|
| RWW Partition 5 | 0x28C00000 | 2048 KB |
|
| RWW Partition 6 | 0x29000000 | 2048 KB |
|
| RWW Partition 7 | 0x29400000 | 2048 KB |
|
| EEPROM / RWW 8 | 0x29E00000 | 512 KB |
|
| UTEST / RWW 1 | 0x29F80000 | 32 KB |
|
| Boot Code Sector / RWW 1 | 0x29FB8000 | 16 KB |
|
| HSM Code / RWW 9/10 | 0x00000000 | 512 KB | 
|
| HSM Data / RWW 11 | 0x003A0000 | 128 KB |
|
| HSM UT / RWW 11 | 0x0037C000 | 16 KB |
|
ECC Flash
Device has ECC Flash, but no special init necessary. Please refer to the reference Manual.
ECC RAM
Device has ECC RAM, init before first use is necessary.
Multi-Core Support [OPTIONAL]
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The SR6P6 family comes with 6 Corext-R52 and 3 Cortex-M4 cores. Some of them are available with enabled lockstep mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-R52 Cluster 0 Core 0
Init/Setup
- Functional Reset is initiated for Cut 1.0 silicon.
- WDT is disabled
Reset
- Cortex-R Reset Pin is performed
- Functional Reset is initiated for Cut 1.0 silicon.
- Initializes the 64KB ECC RAM starting at 0x60000000
- WDT is disabled
Attach
- Attach is supported, user has to take care about ECC RAM initialisation.
Cortex-R52 Cluster 0 Core 1
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- Cortex-R Reset Pin is performed
Attach
- Attach is supported
Cortex-R52 Cluster 1 Core 0
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- Cortex-R Reset Pin is performed
Attach
- Attach is supported
Cortex-R52 Cluster 1 Core 1
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- Cortex-R Reset Pin is performed
Attach
- Attach is supported
Cortex-R52 Cluster 2 Core 0
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- Cortex-R Reset Pin is performed
Attach
- Attach is supported
DSPH Core
Init/Setup
Reset
- Cortex-R Reset Pin is performed
Attach
- Attach is supported
Device Specific Handling
Reset
- The devices uses Cortex-AR Reset Pin, no special handling necessary, like described here.
Evaluation Boards
- ST SR6P6-EVB60000P evaluation board: http://wiki.segger.com/ST_SR6P6-EVBC8000P
