Difference between revisions of "SemiDrive E34xx"
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==ECC RAM== |
==ECC RAM== |
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E34xx devices have ECC RAM which can be disabled. |
E34xx devices have ECC RAM which can be disabled. |
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| − | However, a connect to E34xx devices will initialize 1MB at 0x400000. |
+ | However, a connect to CPU 0 of E34xx devices will initialize 1MB at 0x400000. |
==Reset== |
==Reset== |
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Revision as of 14:41, 7 June 2023
Contents
The SemiDrive E34xx are multicore Cortex-R5 based MCUs. They are composed of two CPU clusters with 3 cores in total. J-Link offers access to each core by using the specific device name. Supported E34xx devices are:
| Device Name | CPU Cluster & Core |
|---|---|
| E3420 | CPU0 |
| E3420_CPU1 | CPU1 Core 0 |
| E3420_CPU2 | CPU1 Core 1 |
| E3430 | CPU0 |
| E3430_CPU1 | CPU1 Core 0 |
| E3430_CPU2 | CPU1 Core 1 |
Internal Flash
E34xx devices have no internal flash.
QSPI Flash
QSPI flashes are not supported by J-Link. Refer to the J-Link Device Support Kit for adding support by yourself.
ECC RAM
E34xx devices have ECC RAM which can be disabled. However, a connect to CPU 0 of E34xx devices will initialize 1MB at 0x400000.
Reset
No device specific reset is necessary. The normal Cortex-R reset is performed.
See here for more information: https://wiki.segger.com/J-Link_Reset_Strategies#Strategies_for_ARMv8-AR_devices
