Difference between revisions of "SemiDrive E36xx"

Revision as of 15:47, 30 May 2023

E34xx devices have no internal flash.

QSPI flashes are not supported by J-Link. Refer to the J-Link Device Support Kit for adding support by yourself.

E36xx devices have ECC RAM which can be disabled. However, a connect to E36xx devices will initialize 1MB at 0x400000.

No device specific reset is necessary. The normal Cortex-R reset is performed.

@@ Line 1: / Line 1: @@
 __TOC__
-The SemiDrive E36xx are Cortex-R5 based MCUs.
+The SemiDrive E36xx are Cortex-R5 based MCUs. They are composed of two CPU clusters with 5 cores in total.
+J-Link offers access to each core by using the specific device name.
+Supported E34xx devices are:
+{| class="seggertable"
+|-
+! Device Name || CPU Cluster & Core
+|-
+| E3640 || CPU0
+|-
+| E3640_CPU1 || CPU1 Core 0
+|-
+| E3640_CPU2 || CPU1 Core 1
+|-
+| E3640_CPU3 || CPU2 Core 0
+|-
+| E3640_CPU4 || CPU2 Core 1
+|-
+| E3640 || CPU0
+|-
+| E3648_CPU1 || CPU1 Core 0
+|-
+| E3648_CPU2 || CPU1 Core 1
+|-
+| E3648_CPU3 || CPU2 Core 0
+|-
+| E3648_CPU4 || CPU2 Core 1
+|-
+|}
 ==Internal Flash==
 E34xx devices have no internal flash.
+==QSPI Flash==
+QSPI flashes are not supported by J-Link.
+Refer to the [[J-Link_Device_Support_Kit | J-Link Device Support Kit]] for adding support by yourself.
 ==ECC RAM==