Difference between revisions of "SiFive S54 Standard Core Dev Kit"

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This article describes specifics for the SiFive S54 Standard Core Dev Kit. The SiFive S54 Standard Core Dev Kit implements a SiFive S54 (64-bit RV64) core as a FPGA bitstream that runs on the Digilent ARTY-100T eval board.
  
This article describes specifics for the SiFive S54 Standard Core Dev Kit. The SiFive S54 Standard Core Dev Kit implements a SiFive S54 (64-bit RV64) core as a FPGA bitstream that runs on the Digilent ARTY-100T eval board.
  +
[[File: ARTY-100T.png | thumb | left]]
  +
<br clear=all>
   
 
= Getting the bitstream running =
  
= Getting the bitstream running =
Line 11: Line 13:
 
* Micro USB cable
  
* Micro USB cable
   
−
After the bitstream has been programmed:
 +
== Programming the bitstream ==
  +
In this article, Vivado LAB 2017.2 was used but the steps should be identical / very similar for later versions.
  +
* Supply power to the ARTY-100T board via the power jack (7V, center positive)
  +
* Connect the ARTY-100T board via micro USB cable to the computer
  +
* Start Vivado LAB
  +
* Click '''Open Hardware Manager'''
  +
*;[[File: ARTY-100T_VivadoLAB_OpenHWManager.png | none]]
  +
* Click '''Open Target -> Auto Connect'''
  +
*;[[File: ARTY-100T_VivadoLAB_OpenTarget.png | none]]
  +
* '''Select FPGA -> Right-click -> Add Configuration Memory Device'''
  +
*;[[File: ARTY-100T_VivadoLAB_AddConfigMem.png | none]]
  +
* Select the appropriate flash device as shown in the screenshot below
  +
*;[[File: ARTY-100T_VivadoLAB_SelFlash.png | none]]
  +
* Confirm the following dialog with '''OK'''
  +
*;[[File: ARTY-100T_VivadoLAB_ConfirmProgram.png | none]]
  +
* Select the MCS file (bitstream) for the S54 from the SiFive dev kit package and set the programming settings<br />as shown in the screenshot below and confirm with '''OK''' afterwards<br />The MCS file for the S54 is located under: sifive_s54_rtl_eval_llama.02.00rc1-general\arty_a7_100t-sifive\design-arty.mcs
  +
*;[[File: ARTY-100T_VivadoLAB_ProgSettings.png | none]]
  +
* Wait for about 30 seconds for programming to complete
  +
* Once programming has finished, confirm the dialog with '''OK'''
  +
*;[[File: ARTY-100T_VivadoLAB_ProgFinished.png | none]]
  +
* Close Vivado LAB
  +
* Push the PROG button on the ARTY-100T board to load the bitstream into the FPGA<br />(Only needed once after programming. Bitstream is auto-loaded on power cycle of board, from now on)
  +
*;[[File: ARTY-100T_PROGButton.png | none]]
  +
* Wait until the DONE LED lights up again.
  +
  +
== Troubleshooting ==
  +
* Vivado LAB '''Auto connect''' fails:
  +
** The ARTY board sports a FTDI FT2232 chip for Flashing the FPGA. You will need to install the VCOM drivers.
  +
** For Windows there is a setup exe which is recommended.
  +
** Before installing make sure nothing is connected via USB.
  +
** Now install the driver.
  +
** Restart the PC
  +
** If everything worked, once you connect USB port J10 from the board to your PC you should have a Composite device in your device manager.
  +
** The Vivado LAB setup may not successfully install on a guest OS inside a virtual machine. It is recommended to install and run Vivado Lab on a native OS.
  +
  +
= Verifying the debug connection =
  +
  +
== Prerequisites ==
 
* J-Link BASE or higher: [https://www.segger.com/products/debug-probes/j-link/models/model-overview/ Model overview]
  
* J-Link BASE or higher: [https://www.segger.com/products/debug-probes/j-link/models/model-overview/ Model overview]
 
* [https://www.segger.com/products/debug-probes/j-link/accessories/adapters/j-link-sifive-arty-adapter/ SEGGER SiFive-ARTY adapter]
  
* [https://www.segger.com/products/debug-probes/j-link/accessories/adapters/j-link-sifive-arty-adapter/ SEGGER SiFive-ARTY adapter]
  +
* [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack J-Link software package V7.22 or later]
   
−
== Programming the bitstream ==
 +
== Connecting to the device ==
−
The MCS file is located under: sifive_s54_rtl_eval_llama.02.00rc1-general\arty_a7_100t-sifive\design-arty.mcs
  
−
For the general procedure to program the bitstream, please follow the steps in this article: [[Program bitstream into AVNET ARTYA7 board]]
  
−  
−
== Verifying the debug connection ==
  
 
* Connect the [https://www.segger.com/products/debug-probes/j-link/accessories/adapters/j-link-sifive-arty-adapter/ SEGGER SiFive-ARTY adapter] to connector JD on the ARTY-100T board
  
* Connect the [https://www.segger.com/products/debug-probes/j-link/accessories/adapters/j-link-sifive-arty-adapter/ SEGGER SiFive-ARTY adapter] to connector JD on the ARTY-100T board
 
* Connect J-Link to the [https://www.segger.com/products/debug-probes/j-link/accessories/adapters/j-link-sifive-arty-adapter/ SEGGER SiFive-ARTY adapter]
  
* Connect J-Link to the [https://www.segger.com/products/debug-probes/j-link/accessories/adapters/j-link-sifive-arty-adapter/ SEGGER SiFive-ARTY adapter]
−
* Start J-Link Commander with device selection '''S54''' and TIF == JTAG and verify the connection.
 +
* Start J-Link Commander with device selection '''S54ARTY''' and TIF == JTAG and verify the connection.
  +
*;[[File: SiFive_S54ARTY_Commander.png | none]]
−
*; <Picture>
  

Latest revision as of 13:01, 21 May 2021

This article describes specifics for the SiFive S54 Standard Core Dev Kit. The SiFive S54 Standard Core Dev Kit implements a SiFive S54 (64-bit RV64) core as a FPGA bitstream that runs on the Digilent ARTY-100T eval board.

ARTY-100T.png


Getting the bitstream running

Prerequisites

To program the bitstream:

  • SiFive S54 Standard Core Dev Kit: sifive.com
  • Digilent ARTY-100T FPGA eval board (~200 EUR)
  • Xilinx Vivado LAB (free)
  • Micro USB cable

Programming the bitstream

In this article, Vivado LAB 2017.2 was used but the steps should be identical / very similar for later versions.

  • Supply power to the ARTY-100T board via the power jack (7V, center positive)
  • Connect the ARTY-100T board via micro USB cable to the computer
  • Start Vivado LAB
  • Click Open Hardware Manager
    ARTY-100T VivadoLAB OpenHWManager.png
  • Click Open Target -> Auto Connect
    ARTY-100T VivadoLAB OpenTarget.png
  • Select FPGA -> Right-click -> Add Configuration Memory Device
    ARTY-100T VivadoLAB AddConfigMem.png
  • Select the appropriate flash device as shown in the screenshot below
    ARTY-100T VivadoLAB SelFlash.png
  • Confirm the following dialog with OK
    ARTY-100T VivadoLAB ConfirmProgram.png
  • Select the MCS file (bitstream) for the S54 from the SiFive dev kit package and set the programming settings
    as shown in the screenshot below and confirm with OK afterwards
    The MCS file for the S54 is located under: sifive_s54_rtl_eval_llama.02.00rc1-general\arty_a7_100t-sifive\design-arty.mcs
    ARTY-100T VivadoLAB ProgSettings.png
  • Wait for about 30 seconds for programming to complete
  • Once programming has finished, confirm the dialog with OK
    ARTY-100T VivadoLAB ProgFinished.png
  • Close Vivado LAB
  • Push the PROG button on the ARTY-100T board to load the bitstream into the FPGA
    (Only needed once after programming. Bitstream is auto-loaded on power cycle of board, from now on)
    ARTY-100T PROGButton.png
  • Wait until the DONE LED lights up again.

Troubleshooting

  • Vivado LAB Auto connect fails:
    • The ARTY board sports a FTDI FT2232 chip for Flashing the FPGA. You will need to install the VCOM drivers.
    • For Windows there is a setup exe which is recommended.
    • Before installing make sure nothing is connected via USB.
    • Now install the driver.
    • Restart the PC
    • If everything worked, once you connect USB port J10 from the board to your PC you should have a Composite device in your device manager.
    • The Vivado LAB setup may not successfully install on a guest OS inside a virtual machine. It is recommended to install and run Vivado Lab on a native OS.

Verifying the debug connection

Prerequisites

Connecting to the device

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