SiFive S54 Standard Core Dev Kit
Contents
This article describes specifics for the SiFive S54 Standard Core Dev Kit. The SiFive S54 Standard Core Dev Kit implements a SiFive S54 (64-bit RV64) core as a FPGA bitstream that runs on the Digilent ARTY-100T eval board.
Getting the bitstream running
Prerequisites
To program the bitstream:
- SiFive S54 Standard Core Dev Kit: sifive.com
- Digilent ARTY-100T FPGA eval board (~200 EUR)
- Xilinx Vivado LAB (free)
- Micro USB cable
After the bitstream has been programmed:
- J-Link BASE or higher: Model overview
- SEGGER SiFive-ARTY adapter
Programming the bitstream
The MCS file is located under: sifive_s54_rtl_eval_llama.02.00rc1-general\arty_a7_100t-sifive\design-arty.mcs For the general procedure to program the bitstream, please follow the steps in this article: Program bitstream into AVNET ARTYA7 board
Verifying the debug connection
- Connect the SEGGER SiFive-ARTY adapter to connector JD on the ARTY-100T board
- Connect J-Link to the SEGGER SiFive-ARTY adapter
- Start J-Link Commander with device selection S54 and TIF == JTAG and verify the connection.
- <Picture>
