Difference between revisions of "Silicon Labs EFR32xG24"
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The device has a watchdog, which is fed during flash programming, if enabled. |
The device has a watchdog, which is fed during flash programming, if enabled. |
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| − | ==Device Specific Handling== |
+ | == Device Specific Handling == |
===Reset=== |
===Reset=== |
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*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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| − | == |
+ | === Security === |
| − | ===Security=== |
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See: [[Silicon Labs EFx32 Series 2#Debug lock | Silicon Labs EFx32 Series 2]] article. |
See: [[Silicon Labs EFx32 Series 2#Debug lock | Silicon Labs EFx32 Series 2]] article. |
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=== Secure boot === |
=== Secure boot === |
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See: [[Silicon Labs EFx32 Series 2#Secure boot specific | Silicon Labs EFx32 Series 2]] article. |
See: [[Silicon Labs EFx32 Series 2#Secure boot specific | Silicon Labs EFx32 Series 2]] article. |
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Latest revision as of 16:31, 10 October 2023
The Silicon Labs EFR32xG24 device family are Cortex-M33 based microcontrollers. These MCUs are part of the EFx32 Series 2 devices.
Contents
EFx32 Series 2 specifics
Please refer to the Silicon Labs EFx32 Series 2 article.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x0800_0000 | Up to 1536 KB | 
|
| User Data | 0x0FE0_0000 | 1 KB |
|
Watchdog Handling
The device has a watchdog, which is fed during flash programming, if enabled.
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
Security
See: Silicon Labs EFx32 Series 2 article.
Secure boot
See: Silicon Labs EFx32 Series 2 article.
